Lines Matching refs:C
330 #define C(x) PERF_COUNT_HW_CACHE_##x macro
337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
341 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = 0,
345 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
349 [ C(RESULT_MISS) ] = 0,
352 [ C(L1I) ] = {
353 [ C(OP_READ) ] = {
354 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
355 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
359 [ C(RESULT_MISS) ] = -1,
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
363 [ C(RESULT_MISS) ] = 0,
366 [ C(LL) ] = {
367 [ C(OP_READ) ] = {
368 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
369 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = 0,
373 [ C(RESULT_MISS) ] = 0,
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
377 [ C(RESULT_MISS) ] = 0,
380 [ C(DTLB) ] = {
381 [ C(OP_READ) ] = {
382 [ C(RESULT_ACCESS) ] = 0,
383 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = -1,
387 [ C(RESULT_MISS) ] = -1,
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = -1,
391 [ C(RESULT_MISS) ] = -1,
394 [ C(ITLB) ] = {
395 [ C(OP_READ) ] = {
396 [ C(RESULT_ACCESS) ] = 0,
397 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
399 [ C(OP_WRITE) ] = {
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = -1,
405 [ C(RESULT_MISS) ] = -1,
408 [ C(BPU) ] = {
409 [ C(OP_READ) ] = {
410 [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
411 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
413 [ C(OP_WRITE) ] = {
414 [ C(RESULT_ACCESS) ] = -1,
415 [ C(RESULT_MISS) ] = -1,
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = -1,
419 [ C(RESULT_MISS) ] = -1,
422 [ C(NODE) ] = {
423 [ C(OP_READ) ] = {
424 [ C(RESULT_ACCESS) ] = -1,
425 [ C(RESULT_MISS) ] = -1,
427 [ C(OP_WRITE) ] = {
428 [ C(RESULT_ACCESS) ] = -1,
429 [ C(RESULT_MISS) ] = -1,
431 [ C(OP_PREFETCH) ] = {
432 [ C(RESULT_ACCESS) ] = -1,
433 [ C(RESULT_MISS) ] = -1,
438 #undef C