mips/kernel/perf_event_mipsxx.c

74 #define C(x) PERF_COUNT_HW_CACHE_##x  macro
1010 [C(L1D)] = {
1017 	[C(OP_READ)] = {
1018 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1019 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1021 	[C(OP_WRITE)] = {
1022 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1023 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1026 [C(L1I)] = {
1027 	[C(OP_READ)] = {
1028 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1029 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
1031 	[C(OP_WRITE)] = {
1032 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1033 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
1035 	[C(OP_PREFETCH)] = {
1036 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
1043 [C(LL)] = {
1044 	[C(OP_READ)] = {
1045 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
1046 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1048 	[C(OP_WRITE)] = {
1049 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
1050 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1053 [C(DTLB)] = {
1054 	[C(OP_READ)] = {
1055 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1056 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1058 	[C(OP_WRITE)] = {
1059 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1060 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1063 [C(ITLB)] = {
1064 	[C(OP_READ)] = {
1065 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1066 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
1068 	[C(OP_WRITE)] = {
1069 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1070 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
1073 [C(BPU)] = {
1075 	[C(OP_READ)] = {
1076 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1077 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1079 	[C(OP_WRITE)] = {
1080 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1081 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1091 [C(L1D)] = {
1098 	[C(OP_READ)] = {
1099 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
1100 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
1102 	[C(OP_WRITE)] = {
1103 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
1104 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
1107 [C(L1I)] = {
1108 	[C(OP_READ)] = {
1109 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1110 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1112 	[C(OP_WRITE)] = {
1113 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1114 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1116 	[C(OP_PREFETCH)] = {
1117 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
1124 [C(LL)] = {
1125 	[C(OP_READ)] = {
1126 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
1127 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1129 	[C(OP_WRITE)] = {
1130 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
1131 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1139 [C(ITLB)] = {
1140 	[C(OP_READ)] = {
1141 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1142 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1144 	[C(OP_WRITE)] = {
1145 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1146 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1149 [C(BPU)] = {
1151 	[C(OP_READ)] = {
1152 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1153 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1155 	[C(OP_WRITE)] = {
1156 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1157 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1166 [C(L1D)] = {
1167 	[C(OP_READ)] = {
1168 		[C(RESULT_ACCESS)]	= { 0x46, CNTR_EVEN | CNTR_ODD },
1169 		[C(RESULT_MISS)]	= { 0x49, CNTR_EVEN | CNTR_ODD },
1171 	[C(OP_WRITE)] = {
1172 		[C(RESULT_ACCESS)]	= { 0x47, CNTR_EVEN | CNTR_ODD },
1173 		[C(RESULT_MISS)]	= { 0x4a, CNTR_EVEN | CNTR_ODD },
1176 [C(L1I)] = {
1177 	[C(OP_READ)] = {
1178 		[C(RESULT_ACCESS)]	= { 0x84, CNTR_EVEN | CNTR_ODD },
1179 		[C(RESULT_MISS)]	= { 0x85, CNTR_EVEN | CNTR_ODD },
1182 [C(DTLB)] = {
1184 	[C(OP_READ)] = {
1185 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1186 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1188 	[C(OP_WRITE)] = {
1189 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1190 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1193 [C(BPU)] = {
1195 	[C(OP_READ)] = {
1196 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_EVEN | CNTR_ODD },
1197 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN | CNTR_ODD },
1206 [C(L1D)] = {
1213 	[C(OP_READ)] = {
1214 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1216 	[C(OP_WRITE)] = {
1217 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1220 [C(L1I)] = {
1221 	[C(OP_READ)] = {
1222 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1224 	[C(OP_WRITE)] = {
1225 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1228 [C(DTLB)] = {
1229 	[C(OP_READ)] = {
1230 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1232 	[C(OP_WRITE)] = {
1233 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1236 [C(ITLB)] = {
1237 	[C(OP_READ)] = {
1238 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1240 	[C(OP_WRITE)] = {
1241 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1244 [C(BPU)] = {
1246 	[C(OP_READ)] = {
1247 		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1248 		[C(RESULT_MISS)]        = { 0x01, CNTR_ODD },
1250 	[C(OP_WRITE)] = {
1251 		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1252 		[C(RESULT_MISS)]        = { 0x01, CNTR_ODD },
1261 [C(L1D)] = {
1268 	[C(OP_READ)] = {
1269 		[C(RESULT_ACCESS)]	= { 0x156, CNTR_ALL },
1271 	[C(OP_WRITE)] = {
1272 		[C(RESULT_ACCESS)]	= { 0x155, CNTR_ALL },
1273 		[C(RESULT_MISS)]        = { 0x153, CNTR_ALL },
1276 [C(L1I)] = {
1277 	[C(OP_READ)] = {
1278 		[C(RESULT_MISS)]	= { 0x18, CNTR_ALL },
1280 	[C(OP_WRITE)] = {
1281 		[C(RESULT_MISS)]        = { 0x18, CNTR_ALL },
1284 [C(LL)] = {
1285 	[C(OP_READ)] = {
1286 		[C(RESULT_ACCESS)]	= { 0x1b6, CNTR_ALL },
1288 	[C(OP_WRITE)] = {
1289 		[C(RESULT_ACCESS)]	= { 0x1b7, CNTR_ALL },
1291 	[C(OP_PREFETCH)] = {
1292 		[C(RESULT_ACCESS)]	= { 0x1bf, CNTR_ALL },
1295 [C(DTLB)] = {
1296 	[C(OP_READ)] = {
1297 		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1299 	[C(OP_WRITE)] = {
1300 		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1303 [C(ITLB)] = {
1304 	[C(OP_READ)] = {
1305 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1307 	[C(OP_WRITE)] = {
1308 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1311 [C(BPU)] = {
1313 	[C(OP_READ)] = {
1314 		[C(RESULT_ACCESS)]      = { 0x94, CNTR_ALL },
1315 		[C(RESULT_MISS)]        = { 0x9c, CNTR_ALL },
1324 [C(L1D)] = {
1331 	[C(OP_READ)] = {
1332 		[C(RESULT_ACCESS)]      = { 0x1e, CNTR_ALL },
1333 		[C(RESULT_MISS)]        = { 0x1f, CNTR_ALL },
1335 	[C(OP_PREFETCH)] = {
1336 		[C(RESULT_ACCESS)]	= { 0xaa, CNTR_ALL },
1337 		[C(RESULT_MISS)]	= { 0xa9, CNTR_ALL },
1340 [C(L1I)] = {
1341 	[C(OP_READ)] = {
1342 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ALL },
1343 		[C(RESULT_MISS)]	= { 0x1d, CNTR_ALL },
1346 [C(LL)] = {
1347 	[C(OP_READ)] = {
1348 		[C(RESULT_ACCESS)]	= { 0x2e, CNTR_ALL },
1349 		[C(RESULT_MISS)]	= { 0x2f, CNTR_ALL },
1352 [C(DTLB)] = {
1353 	[C(OP_READ)] = {
1354 		[C(RESULT_ACCESS)]      = { 0x14, CNTR_ALL },
1355 		[C(RESULT_MISS)]	= { 0x1b, CNTR_ALL },
1358 [C(ITLB)] = {
1359 	[C(OP_READ)] = {
1360 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1363 [C(BPU)] = {
1365 	[C(OP_READ)] = {
1366 		[C(RESULT_ACCESS)]      = { 0x02, CNTR_ALL },
1367 		[C(RESULT_MISS)]        = { 0x08, CNTR_ALL },
1377 [C(L1D)] = {
1384 	[C(OP_READ)] = {
1385 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1386 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1388 	[C(OP_WRITE)] = {
1389 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1390 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1393 [C(L1I)] = {
1394 	[C(OP_READ)] = {
1395 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1396 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1398 	[C(OP_WRITE)] = {
1399 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1400 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1402 	[C(OP_PREFETCH)] = {
1403 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1410 [C(LL)] = {
1411 	[C(OP_READ)] = {
1412 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1413 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1415 	[C(OP_WRITE)] = {
1416 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1417 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1420 [C(BPU)] = {
1422 	[C(OP_READ)] = {
1423 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1425 	[C(OP_WRITE)] = {
1426 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1435 [C(L1D)] = {
1436 	[C(OP_READ)] = {
1437 		[C(RESULT_ACCESS)]	= { 0x2b, CNTR_ALL },
1438 		[C(RESULT_MISS)]	= { 0x2e, CNTR_ALL },
1440 	[C(OP_WRITE)] = {
1441 		[C(RESULT_ACCESS)]	= { 0x30, CNTR_ALL },
1444 [C(L1I)] = {
1445 	[C(OP_READ)] = {
1446 		[C(RESULT_ACCESS)]	= { 0x18, CNTR_ALL },
1448 	[C(OP_PREFETCH)] = {
1449 		[C(RESULT_ACCESS)]	= { 0x19, CNTR_ALL },
1452 [C(DTLB)] = {
1457 	[C(OP_READ)] = {
1458 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1460 	[C(OP_WRITE)] = {
1461 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1464 [C(ITLB)] = {
1465 	[C(OP_READ)] = {
1466 		[C(RESULT_MISS)]	= { 0x37, CNTR_ALL },