drivers/perf/riscv_pmu_sbi.c

155 #define C(x) PERF_COUNT_HW_CACHE_##x  macro
159 	[C(L1D)] = {
160 		[C(OP_READ)] = {
161 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
162 					C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
163 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
164 					C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
166 		[C(OP_WRITE)] = {
167 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
168 					C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
169 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
170 					C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
172 		[C(OP_PREFETCH)] = {
173 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
174 					C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
175 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
176 					C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
179 	[C(L1I)] = {
180 		[C(OP_READ)] = {
181 			[C(RESULT_ACCESS)] = {.hw_cache_event =	{C(RESULT_ACCESS),
182 					C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
183 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
184 					C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
186 		[C(OP_WRITE)] = {
187 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
188 					C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
189 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
190 					C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
192 		[C(OP_PREFETCH)] = {
193 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
194 					C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
195 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
196 					C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
199 	[C(LL)] = {
200 		[C(OP_READ)] = {
201 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
202 					C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
203 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
204 					C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
206 		[C(OP_WRITE)] = {
207 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
208 					C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
209 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
210 					C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
212 		[C(OP_PREFETCH)] = {
213 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
214 					C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
215 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
216 					C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
219 	[C(DTLB)] = {
220 		[C(OP_READ)] = {
221 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
222 					C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
223 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
224 					C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
226 		[C(OP_WRITE)] = {
227 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
228 					C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
229 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
230 					C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
232 		[C(OP_PREFETCH)] = {
233 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
234 					C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
235 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
236 					C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
239 	[C(ITLB)] = {
240 		[C(OP_READ)] = {
241 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
242 					C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
243 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
244 					C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
246 		[C(OP_WRITE)] = {
247 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
248 					C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
249 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
250 					C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
252 		[C(OP_PREFETCH)] = {
253 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
254 					C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
255 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
256 					C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
259 	[C(BPU)] = {
260 		[C(OP_READ)] = {
261 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
262 					C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
263 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
264 					C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
266 		[C(OP_WRITE)] = {
267 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
268 					C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
269 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
270 					C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
272 		[C(OP_PREFETCH)] = {
273 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
274 					C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
275 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
276 					C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
279 	[C(NODE)] = {
280 		[C(OP_READ)] = {
281 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
282 					C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
283 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
284 					C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
286 		[C(OP_WRITE)] = {
287 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
288 					C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
289 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
290 					C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
292 		[C(OP_PREFETCH)] = {
293 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
294 					C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
295 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
296 					C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},