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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
[all …]
Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
[all …]
/linux-6.12.1/sound/soc/atmel/
Datmel_ssc_dai.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC
11 * Based on at91-ssc.c by
21 #include <linux/atmel-ssc.h>
23 #include "atmel-pcm.h"
25 /* SSC system clock ids */
26 #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */
33 * SSC direction masks
40 * SSC register values that Atmel left out of <linux/atmel-ssc.h>. These
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am62x-sk-hdmi-audio.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Audio playback via HDMI for AM625-SK and AM62-LP SK.
6 * AM625 SK: https://www.ti.com/tool/SK-AM62
7 * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP
9 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
12 /dts-v1/;
16 hdmi_audio: sound-sii9022 {
17 compatible = "simple-audio-card";
18 simple-audio-card,name = "AM62x-Sil9022-HDMI";
19 simple-audio-card,format = "i2s";
[all …]
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-timecard18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
83 for internal disciplining of the atomic clock.
89 for internal disciplining of the atomic clock.
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mn-beacon-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include "imx8mn-beacon-som.dtsi"
10 #include "imx8mn-beacon-baseboard.dtsi"
14 compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn";
17 stdout-path = &uart2;
21 compatible = "hdmi-connector";
26 remote-endpoint = <&adv7535_out>;
31 reg_hdmi: regulator-hdmi-dvdd {
32 compatible = "regulator-fixed";
[all …]
Dimx8mm-beacon-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include "imx8mm-beacon-som.dtsi"
10 #include "imx8mm-beacon-baseboard.dtsi"
14 compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm";
17 stdout-path = &uart2;
21 compatible = "hdmi-connector";
26 remote-endpoint = <&adv7535_out>;
31 reg_hdmi: regulator-hdmi-dvdd {
32 compatible = "regulator-fixed";
[all …]
Dimx8mp-beacon-kit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 #include "imx8mp-beacon-som.dtsi"
15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
23 stdout-path = &uart2;
26 clk_xtal25: clock-xtal25 {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
[all …]
/linux-6.12.1/arch/m68k/include/asm/
DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
[all …]
DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
34 * System Control Register (SCR)
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
[all …]
DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
32 * System Control Register (SCR)
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
[all …]
/linux-6.12.1/Documentation/spi/
Dspi-summary.rst5 02-Feb-2012
8 ------------
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
16 Slave Out" (MISO) signals. (Other names are also used.) There are four
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2g-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
25 dsp_common_memory: dsp-common-memory@81f800000 {
26 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/drivers/media/usb/dvb-usb-v2/
Drtl28xxu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
138 * 0x3000 SYS : system
146 #define USB_SYSCTL 0x2000 /* USB system control */
147 #define USB_SYSCTL_0 0x2000 /* USB system control */
148 #define USB_SYSCTL_1 0x2001 /* USB system control */
149 #define USB_SYSCTL_2 0x2002 /* USB system control */
150 #define USB_SYSCTL_3 0x2003 /* USB system control */
196 #define USB_TOUT_VAL 0x2F08 /* USB time-out time */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
209 #define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */
[all …]
/linux-6.12.1/Documentation/scsi/
DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
[all …]
/linux-6.12.1/sound/soc/fsl/
Dfsl_esai.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
33 * struct fsl_esai - ESAI private data
38 * @coreclk: clock source to access register
39 * @extalclk: esai clock source to derive HCK, SCK and FS
40 * @fsysclk: system clock source to derive HCK, SCK and FS
41 * @spbaclk: SPBA clock (optional, depending on SoC design)
51 * @hck_rate: clock rate of desired HCKx clock
52 * @sck_rate: clock rate of desired SCKx clock
[all …]
/linux-6.12.1/arch/arm/boot/dts/cirrus/
Dep93xx-edb9302.dts1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
5 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
27 compatible = "audio-graph-card2";
33 compatible = "gpio-leds";
34 led-0 {
37 linux,default-trigger = "heartbeat";
41 led-1 {
55 compatible = "cfi-flash";
[all …]
/linux-6.12.1/Documentation/driver-api/
Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
11 signal of a device with an external clock signal. Effectively enabling
12 device to run on the same clock signal beat as provided on a PLL input.
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
41 configuration of particular device in the system. It can be obtained
57 system with `dump` request of ``DPLL_CMD_PIN_GET`` command.
61 configuration of particular pin in the system. It can be obtained with
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
15 #include <linux/i2c-smbus.h>
49 * baud clock required to program 'Hold Time' at X KHz.
65 * the baud clock required to program 'fair idle delay' at X KHz. Fair idle
74 * baud clock required to satisfy the fairness protocol at X KHz.
103 * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock
104 * periods that make up the low phase of the I2C/SMBus bus clock at X KHz.
111 * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock
112 * periods that make up the high phase of the I2C/SMBus bus clock at X KHz.
[all …]
/linux-6.12.1/sound/pci/ice1712/
Denvy24ht.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
49 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
60 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
65 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
96 #define VT1724_I2C_WRITE 0x01 /* write direction */
106 bit3 - during reset used for Eeprom power-on strapping
109 #define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
114 * Professional multi-track direct control registers
117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
[all …]
Dquartet.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 unsigned int scr; /* system control register */
51 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
52 "Word Clock 256xFS"};
65 /* GPIO0 - O - DATA0, def. 0 */
67 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
69 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
71 /* GPIO3 - I/O - DATA3, def. 1 */
73 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
75 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
[all …]
/linux-6.12.1/Documentation/ABI/stable/
Dsysfs-driver-mlxreg-io1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
24 Description: This file shows the system fans direction:
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
30 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
39 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
[all …]
/linux-6.12.1/drivers/macintosh/
Dvia-cuda.c1 // SPDX-License-Identifier: GPL-2.0
3 * Device driver for the Cuda and Egret system controllers found on PowerMacs
7 * This MCU controls system power, Parameter RAM, Real Time Clock and the
38 /* VIA registers - spaced 0x200 bytes apart */
40 #define B 0 /* B-side data */
41 #define A RS /* A-side data */
42 #define DIRB (2*RS) /* B-side direction (1=output) */
43 #define DIRA (3*RS) /* A-side direction (1=output) */
55 #define ANH (15*RS) /* A-side data, no handshake */
62 * ----------------+------------------------------------------
[all …]
/linux-6.12.1/include/linux/soundwire/
Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
75 * enum sdw_slave_status - Slave status
89 * enum sdw_clk_stop_type: clock stop operations
91 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
92 * @SDW_CLK_POST_PREPARE: post clock stop prepare
93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
104 * enum sdw_command_response - Command response as defined by SDW spec
152 * enum sdw_data_direction: Data direction
[all …]
/linux-6.12.1/include/ufs/
Dufshcd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
19 #include <linux/fault-inject.h>
23 #include <linux/dma-direction.h>
68 * struct uic_command - UIC command structure
92 /* Host <-> Device UniPro Link state */
100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
[all …]

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