include/ufs/ufshcd.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
19 #include <linux/fault-inject.h>
23 #include <linux/dma-direction.h>
68  * struct uic_command - UIC command structure
92 /* Host <-> Device UniPro Link state */
100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
103 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
105 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
107 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
110 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
112 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
116 	((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
118 	((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
120 	((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
122 	((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
124 	((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
126 	((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
128 	((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
130 	((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
155  * struct ufshcd_lrb - local reference block
174  * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
194 	u8 lun; /* UPIU LUN id field is only 8-bit wide */
209  * struct ufs_query_req - parameters for building a query request
219  * struct ufs_query_resp - UPIU QUERY
228  * struct ufs_query - holds relevant data structures for query request
240  * struct ufs_dev_cmd - all assosiated fields with device management commands
241  * @type: device management command type - Query, NOP OUT
254  * struct ufs_clk_info - UFS clock related info
255  * @list: list headed by hba->clk_list_head
256  * @clk: clock node
257  * @name: clock name
258  * @max_freq: maximum frequency supported by the clock
259  * @min_freq: min frequency that can be used for clock scaling
297  * struct ufs_hba_variant_ops - variant specific callbacks
306  *                     variant specific Uni-Pro initialization.
307  * @link_startup_notify: called before and after Link startup is carried out
308  *                       to allow variant specific Uni-Pro initialization.
310  *			is carried out to allow vendor spesific capabilities
324  * @config_scaling_param: called to configure clock scaling parameters
326  * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
388 /* clock gating state  */
397  * struct ufs_clk_gating - UFS clock gating related info
407  * @enable_attr: sysfs attribute to enable/disable clock gating
408  * @is_enabled: Indicates the current status of clock gating
409  * @is_initialized: Indicates whether clock gating is initialized or not
412  * @clk_gating_workq: workqueue for clock gating work.
429  * struct ufs_clk_scaling - UFS clock scaling related data
431  * devfreq ->target() function is called then schedule "suspend_work" to
436  * @enable_attr: sysfs attribute to enable/disable clock scaling
447  *		clock scaling which is not invoked from devfreq governor
448  * @is_initialized: Indicates whether clock scaling is initialized or not
474  * struct ufs_event_hist - keeps history of errors
488  * struct ufs_stats - keeps usage/err statistics
492  *		reset this after link-startup.
507  * enum ufshcd_state - UFS host controller state
599 	 * auto-hibernate capability but it doesn't work.
628 	 * 64-bit addressing supported capability but it doesn't work.
634 	 * auto-hibernate capability but it's FASTAUTO only.
711 	 * This capability allows the device auto-bkops to be always enabled
727 	 * This capability allows the host controller driver to turn-on
741 	 * lpm mode aggressively during clock gating.
749 	 * support device hardware reset via the hba->device_reset() callback,
761 	 * Enable WriteBooster when scaling up the clock and disable
762 	 * WriteBooster when scaling the clock down.
794  * struct ufshcd_res_info_t - MCQ related resource regions
818  * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
839  * struct ufs_hba - per adapter private structure
854  * @spm_lvl: desired UFS power management level during system PM.
856  * @ahit: value of Auto-Hibernate Idle Timer register.
864  * @nortt - Max outstanding RTTs supported by controller
874  * @dev_ref_clk_freq: reference clock frequency
906  * @nop_out_timeout: NOP OUT timeout value
913  * @lanes_per_direction: number of lanes per data direction between the UFS
917  * @clk_gating: information related to clock gating
921  * @system_suspending: system suspend has been started and system resume has
923  * @is_sys_suspended: UFS device has been suspended because of system suspend
928  * @clk_scaling_lock: used to serialize device commands and clock scaling
988 	/* Desired UFS power management level during system PM */
992 	/* Auto-Hibernate Idle Timer register value */
1135  * struct ufs_hw_queue - per hardware queue structure
1179 	return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;  in ufshcd_mcq_opr_offset()
1190 	return hba->sg_entry_size;  in ufshcd_sg_entry_size()
1196 	hba->sg_entry_size = sg_entry_size;  in ufshcd_set_sg_entry_size()
1216 	return hba->caps & UFSHCD_CAP_CLK_GATING;  in ufshcd_is_clkgating_allowed()
1220 	return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;  in ufshcd_can_hibern8_during_gating()
1224 	return hba->caps & UFSHCD_CAP_CLK_SCALING;  in ufshcd_is_clkscaling_supported()
1228 	return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;  in ufshcd_can_autobkops_during_suspend()
1232 	return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;  in ufshcd_is_rpm_autosuspend_allowed()
1237 	return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&  in ufshcd_is_intr_aggr_allowed()
1238 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);  in ufshcd_is_intr_aggr_allowed()
1244 		  (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));  in ufshcd_can_aggressive_pc()
1249 	return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&  in ufshcd_is_auto_hibern8_supported()
1250 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);  in ufshcd_is_auto_hibern8_supported()
1255 	return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);  in ufshcd_is_auto_hibern8_enabled()
1260 	return hba->caps & UFSHCD_CAP_WB_EN;  in ufshcd_is_wb_allowed()
1265 	return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;  in ufshcd_enable_wb_if_scaling_up()
1269 	writel((val), (hba)->mcq_base + (reg))
1271 	readl((hba)->mcq_base + (reg))
1274 	writel_relaxed((val), (hba)->mcq_base + (reg))
1276 	readl_relaxed((hba)->mcq_base + (reg))
1279 	writel((val), (hba)->mmio_base + (reg))
1281 	readl((hba)->mmio_base + (reg))
1284  * ufshcd_rmwl - perform read/modify/write for a controller register
1331  * ufshcd_set_variant - set variant specific data to the hba
1338 	hba->priv = variant;  in ufshcd_set_variant()
1342  * ufshcd_get_variant - get variant specific data from the hba
1348 	return hba->priv;  in ufshcd_get_variant()
1422 	return (pwr_info->pwr_rx == FAST_MODE ||  in ufshcd_is_hs_mode()
1423 		pwr_info->pwr_rx == FASTAUTO_MODE) &&  in ufshcd_is_hs_mode()
1424 		(pwr_info->pwr_tx == FAST_MODE ||  in ufshcd_is_hs_mode()
1425 		pwr_info->pwr_tx == FASTAUTO_MODE);  in ufshcd_is_hs_mode()
1466 	if (hba->vops && hba->vops->init)  in ufshcd_vops_init()
1467 		return hba->vops->init(hba);  in ufshcd_vops_init()
1474 	if (hba->vops && hba->vops->phy_initialization)  in ufshcd_vops_phy_initialization()
1475 		return hba->vops->phy_initialization(hba);  in ufshcd_vops_phy_initialization()