Lines Matching +full:system +full:- +full:clock +full:- +full:direction +full:- +full:out
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
34 * System Control Register (SCR)
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
86 #define CSA_EN 0x0001 /* Chip-Select Enable */
87 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
93 #define CSA_RO 0x8000 /* Read-Only */
95 #define CSB_EN 0x0001 /* Chip-Select Enable */
96 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
106 #define CSB_RO 0x8000 /* Read-Only */
108 #define CSC_EN 0x0001 /* Chip-Select Enable */
109 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
119 #define CSC_RO 0x8000 /* Read-Only */
121 #define CSD_EN 0x0001 /* Chip-Select Enable */
122 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
134 #define CSD_RO 0x8000 /* Read-Only */
137 * Emulation Chip-Select Register
147 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
158 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
160 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
162 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
165 /* '328-compatible definitions */
180 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
188 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
194 * 0xFFFFF3xx -- Interrupt Controller
239 #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
245 #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
257 /* '328-compatible definitions */
271 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
284 /* '328-compatible definitions */
300 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
313 /* '328-compatible definitions */
329 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
342 /* '328-compatible definitions */
348 * 0xFFFFF4xx -- Parallel Ports
355 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
357 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
368 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
370 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
392 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
394 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
416 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
418 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
448 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
450 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
472 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
474 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
496 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
498 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
518 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
520 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
533 #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
535 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
555 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
557 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
579 #define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
581 #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
600 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
610 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
618 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
620 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
622 /* '328-compatible definitions */
645 * 0xFFFFF6xx -- General-Purpose Timer
656 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
661 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
667 #define TCTL_FRR 0x0010 /* Free-Run Mode */
669 /* '328-compatible definitions */
679 /* '328-compatible definitions */
689 /* '328-compatible definitions */
699 /* '328-compatible definitions */
709 /* '328-compatible definitions */
722 /* '328-compatible definitions */
728 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
747 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
755 /* '328-compatible definitions */
761 * 0xFFFFF9xx -- UART
776 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
780 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
784 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
789 /* '328-compatible definitions */
808 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
813 #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
832 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
855 /* '328-compatible definitions */
868 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
875 #define UMISC_CLKSRC 0x4000 /* Clock Source */
879 * UART Non-integer Prescaler Register
888 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
920 * 0xFFFFFAxx -- LCD Controller
930 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
944 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
952 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
1002 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
1023 * LACD (LCD Alternate Crystal Direction) Rate Control Register
1029 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1033 * LCD Pixel Clock Divider Register
1038 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1047 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
1052 /* '328-compatible definitions */
1102 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1104 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1105 #define PWMR_SRC_LCD 0x4000 /* LCD clock */
1109 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1160 /* '328-compatible definitions */
1170 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1171 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1173 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1175 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1192 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1194 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1196 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1235 * 0xFFFFFCxx -- DRAM Controller
1271 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1275 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1284 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1285 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1293 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1346 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */