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/linux-6.12.1/drivers/reset/
Dreset-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
20 * @reset_mask: reset mask to use for toggling reset
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/keystone/
Dti,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
27 specific functionality such as clocks, power domain, reset or additional
29 relationship between the TI-SCI parent node to the child node.
[all …]
Dti,k3-sci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common K3 TI-SCI
10 - Nishanth Menon <nm@ti.com>
14 that is responsible for managing various SoC-level resources like clocks,
16 through the TI-SCI protocol.
18 Each specific device management node like a clock controller node, a reset
19 controller node or an interrupt-controller node should define a common set
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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dti,sci-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
17 through a protocol called TI System Control Interface (TI-SCI protocol).
19 This reset controller node uses the TI SCI protocol to perform the reset
21 node of the associated TI-SCI system controller node.
25 pattern: "^reset-controller$"
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/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
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Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-j784s4-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
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Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
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Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
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Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
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Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
31 - ti,am62a-c7xv-dsp
[all …]
Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
40 - ti,am62-r5fss
[all …]
/linux-6.12.1/drivers/remoteproc/
Dti_k3_m4_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI K3 Cortex-M4 Remote Processor(s) driver
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
16 #include <linux/reset.h>
27 * struct k3_m4_rproc_mem - internal memory structure
41 * struct k3_m4_rproc_mem_data - memory definitions for a remote processor
51 * struct k3_m4_rproc - k3 remote processor driver structure
57 * @reset: reset control handle
58 * @tsp: TI-SCI processor control handle
59 * @ti_sci: TI-SCI handle
[all …]
Dti_k3_dsp_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
14 #include <linux/omap-mailbox.h>
17 #include <linux/reset.h>
24 #define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1)
27 * struct k3_dsp_mem - internal memory structure
41 * struct k3_dsp_mem_data - memory definitions for a DSP
51 * struct k3_dsp_dev_data - device data structure for a DSP
55 * @uses_lreset: flag to denote the need for local reset management
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
34 * Default rate for the root input clock, reset this with clk_set_rate()
43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()
115 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP77]),
116 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP77]),
117 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP77]),
118 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP77]),
119 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP77]),
120 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP77]),
[all …]
Dclock-sh7269.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
31 * Default rate for the root input clock, reset this with clk_set_rate()
40 return clk->parent->rate * PLL_RATE; in pll_recalc()
55 return clk->parent->rate / 8; in peripheral0_recalc()
70 return clk->parent->rate / 4; in peripheral1_recalc()
150 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP47]),
151 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP46]),
152 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP45]),
153 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP44]),
[all …]
/linux-6.12.1/drivers/scsi/isci/
Disci.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
118 * enum sci_status - This is the general return status enumeration for non-IO,
119 * non-task management related SCI interface methods.
171 * This member indicates that the SCI implementation is unable to complete
222 * requested information type is not supported by the SCI implementation.
240 * requested information type is not supported by the SCI implementation.
245 * This member indicates the calling function failed, because the SCI
251 * This member indicates the calling method failed, because the SCI
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dclock-sh7785.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c
7 * Copyright (C) 2007 - 2010 Paul Mundt
20 * Default rate for the root input clock, reset this with clk_set_rate()
33 return clk->parent->rate * multiplier; in pll_recalc()
132 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
133 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
134 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
135 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
136 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
[all …]
Dclock-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
18 * Default rate for the root input clock, reset this with clk_set_rate()
35 return clk->parent->rate * multiplier; in pll_recalc()
139 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
140 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
141 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
142 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
143 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
144 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
[all …]
Dclock-shx3.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
5 * SH-X3 support for the clock framework
7 * Copyright (C) 2006-2007 Renesas Technology Corp.
8 * Copyright (C) 2006-2007 Renesas Solutions Corp.
9 * Copyright (C) 2006-2010 Paul Mundt
19 * Default rate for the root input clock, reset this with clk_set_rate()
29 return clk->parent->rate * 72; in pll_recalc()
114 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
115 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
[all …]

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