cpu/sh2a/clock-sh7264.c

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
34  * Default rate for the root input clock, reset this with clk_set_rate()
43 	unsigned long rate = clk->parent->rate / pll1_div;  in pll_recalc()
115 	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP77]),
116 	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP77]),
117 	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP77]),
118 	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP77]),
119 	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP77]),
120 	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP77]),
121 	CLKDEV_ICK_ID("fck", "sh-sci.6", &mstp_clks[MSTP77]),
122 	CLKDEV_ICK_ID("fck", "sh-sci.7", &mstp_clks[MSTP77]),
124 	CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
126 	CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),