cpu/sh4a/clock-sh7786.c

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
18  * Default rate for the root input clock, reset this with clk_set_rate()
35 	return clk->parent->rate * multiplier;  in pll_recalc()
139 	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
140 	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
141 	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
142 	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
143 	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
144 	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
155 	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
156 	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
157 	CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
158 	CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),