cpu/sh2a/clock-sh7269.c

1 // SPDX-License-Identifier: GPL-2.0
3  * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
31  * Default rate for the root input clock, reset this with clk_set_rate()
40 	return clk->parent->rate * PLL_RATE;  in pll_recalc()
55 	return clk->parent->rate / 8;  in peripheral0_recalc()
70 	return clk->parent->rate / 4;  in peripheral1_recalc()
150 	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP47]),
151 	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP46]),
152 	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP45]),
153 	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP44]),
154 	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP43]),
155 	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP42]),
156 	CLKDEV_ICK_ID("fck", "sh-sci.6", &mstp_clks[MSTP41]),
157 	CLKDEV_ICK_ID("fck", "sh-sci.7", &mstp_clks[MSTP40]),
158 	CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
160 	CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),