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/linux-6.12.1/drivers/media/i2c/
Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
[all …]
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
25 /* CCS PLL flags */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
42 * @pll_multiplier: PLL multiplier
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
[all …]
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
/linux-6.12.1/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
10 * integrates this PLL; thus the register structure and programming
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
[all …]
/linux-6.12.1/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-fracn-gppll.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
77 * The (Fref / rdiv) should be in range 20MHz to 40MHz
78 * The Fvco should be in range 2.5Ghz to 5Ghz
103 * The (Fref / rdiv) should be in range 20MHz to 40MHz
104 * The Fvco should be in range 2.5Ghz to 5Ghz
125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) in imx_get_pll_settings() argument
127 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
130 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
140 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); in clk_fracn_gppll_round_rate() local
[all …]
Dclk-frac-pll.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the fractional plls found in the imx8m SOCs
7 * Documentation for this fractional pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
44 static int clk_wait_lock(struct clk_frac_pll *pll) in clk_wait_lock() argument
48 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, in clk_wait_lock()
52 static int clk_wait_ack(struct clk_frac_pll *pll) in clk_wait_ack() argument
56 /* return directly if the pll is in powerdown or in bypass */ in clk_wait_ack()
57 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) in clk_wait_ack()
[all …]
Dclk-pll14xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
92 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
94 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
97 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ in pll1443x_calc_kdiv()
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
129 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, in imx_pll14xx_calc_settings() argument
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/linux-6.12.1/drivers/clk/keystone/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
27 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
29 * @phy_pllm: Physical address of PLLM in pll controller. Used when
31 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
32 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dti,pcm512x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
[all …]
/linux-6.12.1/drivers/clk/sophgo/
Dclk-sg2042-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PLL clock Driver
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
20 #include "clk-sg2042.h"
22 /* Registers defined in SYS_CTRL */
24 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
25 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
26 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
27 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
[all …]
/linux-6.12.1/drivers/staging/sm750fb/
Dddk750_chip.c1 // SPDX-License-Identifier: GPL-2.0
24 /* SM750 and SM750LE are different in their revision ID only. */ in sm750_set_chip_type()
58 struct pll_value pll; in set_chip_clock() local
66 * Set up PLL structure to hold the value to be set in clocks. in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
69 pll.clock_type = MXCLK_PLL; in set_chip_clock()
73 * of the PLL structure. Sometimes, the chip cannot set in set_chip_clock()
78 sm750_calc_pll_value(frequency, &pll); in set_chip_clock()
81 poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll)); in set_chip_clock()
107 /* Set the corresponding divisor in the register. */ in set_memory_clock()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_clear_response_ready_flag()
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
[all …]
Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
6 * to deal in the Software without restriction, including without limitation
12 * paragraph) shall be included in all copies or substantial portions of the
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
48 * enum intel_dpll_id - possible DPLL ids
[all …]
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
6 * to deal in the Software without restriction, including without limitation
12 * paragraph) shall be included in all copies or substantial portions of the
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
45 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
46 * from a pool. In the latter scenario, it is possible that multiple pipes
47 * share a PLL if their configurations match.
[all …]
/linux-6.12.1/drivers/clk/zynq/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
13 can be found in [1].
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
[all …]
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
[all …]
/linux-6.12.1/drivers/clk/ingenic/
Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
20 * @rate_multiplier: the multiplier needed by pll rate calculation
22 * index of the lowest bit of the multiplier value in the PLL's
24 * @m_bits: the size of the multiplier field in bits
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
28 * index of the lowest bit of the divider value in the PLL's
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
/linux-6.12.1/drivers/clk/rockchip/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
71 /* Assumming rate_table is in descending order */ in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
[all …]

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