1 // SPDX-License-Identifier: GPL-2.0-only
3  * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 			 struct aptina_pll *pll)  in aptina_pll_calculate()  argument
26 	dev_dbg(dev, "PLL: ext clock %u pix clock %u\n",  in aptina_pll_calculate()
27 		pll->ext_clock, pll->pix_clock);  in aptina_pll_calculate()
29 	if (pll->ext_clock < limits->ext_clock_min ||  in aptina_pll_calculate()
30 	    pll->ext_clock > limits->ext_clock_max) {  in aptina_pll_calculate()
31 		dev_err(dev, "pll: invalid external clock frequency.\n");  in aptina_pll_calculate()
32 		return -EINVAL;  in aptina_pll_calculate()
35 	if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) {  in aptina_pll_calculate()
36 		dev_err(dev, "pll: invalid pixel clock frequency.\n");  in aptina_pll_calculate()
37 		return -EINVAL;  in aptina_pll_calculate()
41 	div = gcd(pll->pix_clock, pll->ext_clock);  in aptina_pll_calculate()
42 	pll->m = pll->pix_clock / div;  in aptina_pll_calculate()
43 	div = pll->ext_clock / div;  in aptina_pll_calculate()
45 	/* We now have the smallest M and N*P1 values that will result in the  in aptina_pll_calculate()
50 	 * - minimum/maximum multiplier  in aptina_pll_calculate()
51 	 * - minimum/maximum multiplier output clock frequency assuming the  in aptina_pll_calculate()
53 	 * - minimum/maximum combined N*P1 divisor  in aptina_pll_calculate()
55 	mf_min = DIV_ROUND_UP(limits->m_min, pll->m);  in aptina_pll_calculate()
56 	mf_min = max(mf_min, limits->out_clock_min /  in aptina_pll_calculate()
57 		     (pll->ext_clock / limits->n_min * pll->m));  in aptina_pll_calculate()
58 	mf_min = max(mf_min, limits->n_min * limits->p1_min / div);  in aptina_pll_calculate()
59 	mf_max = limits->m_max / pll->m;  in aptina_pll_calculate()
60 	mf_max = min(mf_max, limits->out_clock_max /  in aptina_pll_calculate()
61 		    (pll->ext_clock / limits->n_max * pll->m));  in aptina_pll_calculate()
62 	mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div));  in aptina_pll_calculate()
64 	dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max);  in aptina_pll_calculate()
66 		dev_err(dev, "pll: no valid combined N*P1 divisor.\n");  in aptina_pll_calculate()
67 		return -EINVAL;  in aptina_pll_calculate()
74 	 * 1. p1 is in the [p1_min, p1_max] range given by the limits and is  in aptina_pll_calculate()
76 	 * 2. mf is in the [mf_min, mf_max] range computed above  in aptina_pll_calculate()
77 	 * 3. div * mf is a multiple of p1, in order to compute  in aptina_pll_calculate()
79 	 *	m = pll->m * mf  in aptina_pll_calculate()
80 	 * 4. the internal clock frequency, given by ext_clock / n, is in the  in aptina_pll_calculate()
82 	 * 5. the output clock frequency, given by ext_clock / n * m, is in the  in aptina_pll_calculate()
90 	 * Instead of iterating over all mf values in the [mf_min, mf_max] range  in aptina_pll_calculate()
119 	 * range is not empty, any value in the mf range is acceptable. We thus  in aptina_pll_calculate()
122 	if (limits->p1_min == 0) {  in aptina_pll_calculate()
123 		dev_err(dev, "pll: P1 minimum value must be >0.\n");  in aptina_pll_calculate()
124 		return -EINVAL;  in aptina_pll_calculate()
127 	p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div,  in aptina_pll_calculate()
128 		     pll->ext_clock * pll->m));  in aptina_pll_calculate()
129 	p1_max = min(limits->p1_max, limits->out_clock_max * div /  in aptina_pll_calculate()
130 		     (pll->ext_clock * pll->m));  in aptina_pll_calculate()
132 	for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) {  in aptina_pll_calculate()
137 		mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1,  in aptina_pll_calculate()
138 					limits->int_clock_max * div)), mf_inc);  in aptina_pll_calculate()
139 		mf_high = min(mf_max, pll->ext_clock * p1 /  in aptina_pll_calculate()
140 			      (limits->int_clock_min * div));  in aptina_pll_calculate()
145 		pll->n = div * mf_low / p1;  in aptina_pll_calculate()
146 		pll->m *= mf_low;  in aptina_pll_calculate()
147 		pll->p1 = p1;  in aptina_pll_calculate()
148 		dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1);  in aptina_pll_calculate()
152 	dev_err(dev, "pll: no valid N and P1 divisors found.\n");  in aptina_pll_calculate()
153 	return -EINVAL;  in aptina_pll_calculate()
157 MODULE_DESCRIPTION("Aptina PLL Helpers");