1 // SPDX-License-Identifier: GPL-2.0-only
3  * Zynq PLL driver
10 #include <linux/clk-provider.h>
15  * struct zynq_pll - pll clock
16  * @hw:		Handle between common and hardware-specific interfaces
17  * @pll_ctrl:	PLL control register
18  * @pll_status:	PLL status register
20  * @lockbit:	Indicates the associated PLL_LOCKED bit in the PLL status
45  * zynq_pll_round_rate() - Round a clock frequency
46  * @hw:		Handle between common and hardware-specific interfaces
66  * zynq_pll_recalc_rate() - Recalculate clock frequency
67  * @hw:			Handle between common and hardware-specific interfaces
78 	 * makes probably sense to redundantly save fbdiv in the struct  in zynq_pll_recalc_rate()
81 	fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>  in zynq_pll_recalc_rate()
88  * zynq_pll_is_enabled - Check if a clock is enabled
89  * @hw:		Handle between common and hardware-specific interfaces
101 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_is_enabled()
103 	reg = readl(clk->pll_ctrl);  in zynq_pll_is_enabled()
105 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_is_enabled()
111  * zynq_pll_enable - Enable clock
112  * @hw:		Handle between common and hardware-specific interfaces
124 	pr_info("PLL: enable\n");  in zynq_pll_enable()
126 	/* Power up PLL and wait for lock */  in zynq_pll_enable()
127 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_enable()
129 	reg = readl(clk->pll_ctrl);  in zynq_pll_enable()
131 	writel(reg, clk->pll_ctrl);  in zynq_pll_enable()
132 	while (!(readl(clk->pll_status) & (1 << clk->lockbit)))  in zynq_pll_enable()
135 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_enable()
141  * zynq_pll_disable - Disable clock
142  * @hw:		Handle between common and hardware-specific interfaces
154 	pr_info("PLL: shutdown\n");  in zynq_pll_disable()
156 	/* shut down PLL */  in zynq_pll_disable()
157 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_disable()
159 	reg = readl(clk->pll_ctrl);  in zynq_pll_disable()
161 	writel(reg, clk->pll_ctrl);  in zynq_pll_disable()
163 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_disable()
175  * clk_register_zynq_pll() - Register PLL with the clock framework
176  * @name:	PLL name
178  * @pll_ctrl:	Pointer to PLL control register
179  * @pll_status:	Pointer to PLL status register
180  * @lock_index:	Bit index to this PLL's lock status bit in @pll_status
188 	struct zynq_pll *pll;  in clk_register_zynq_pll()  local
201 	pll = kmalloc(sizeof(*pll), GFP_KERNEL);  in clk_register_zynq_pll()
202 	if (!pll)  in clk_register_zynq_pll()
203 		return ERR_PTR(-ENOMEM);  in clk_register_zynq_pll()
206 	pll->hw.init = &initd;  in clk_register_zynq_pll()
207 	pll->pll_ctrl = pll_ctrl;  in clk_register_zynq_pll()
208 	pll->pll_status = pll_status;  in clk_register_zynq_pll()
209 	pll->lockbit = lock_index;  in clk_register_zynq_pll()
210 	pll->lock = lock;  in clk_register_zynq_pll()
212 	spin_lock_irqsave(pll->lock, flags);  in clk_register_zynq_pll()
214 	reg = readl(pll->pll_ctrl);  in clk_register_zynq_pll()
216 	writel(reg, pll->pll_ctrl);  in clk_register_zynq_pll()
218 	spin_unlock_irqrestore(pll->lock, flags);  in clk_register_zynq_pll()
220 	clk = clk_register(NULL, &pll->hw);  in clk_register_zynq_pll()
227 	kfree(pll);  in clk_register_zynq_pll()