clk/ingenic/cgu.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5  * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18  * struct ingenic_cgu_pll_info - information about a PLL
19  * @reg: the offset of the PLL's control register within the CGU
20  * @rate_multiplier: the multiplier needed by pll rate calculation
22  *           index of the lowest bit of the multiplier value in the PLL's
24  * @m_bits: the size of the multiplier field in bits
25  * @m_offset: the multiplier value which encodes to 0 in the PLL's control
28  *           index of the lowest bit of the divider value in the PLL's
30  * @n_bits: the size of the divider field in bits
31  * @n_offset: the divider value which encodes to 0 in the PLL's control
33  * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34  *            the index of the lowest bit of the post-VCO divider value in
35  *            the PLL's control register)
36  * @od_bits: the size of the post-VCO divider field in bits, or 0 if no
38  * @od_max: the maximum post-VCO divider value
39  * @od_encoding: a pointer to an array mapping post-VCO divider values to
40  *               their encoded values in the PLL control register, or -1 for
43  * @bypass_bit: the index of the bypass bit in the PLL control register, or
44  *              -1 if there is no bypass bit
45  * @enable_bit: the index of the enable bit in the PLL control register, or
46  *		-1 if there is no enable bit (ie, the PLL is always on)
47  * @stable_bit: the index of the stable bit in the PLL control register, or
48  *		-1 if there is no stable bit
71  * struct ingenic_cgu_mux_info - information about a clock mux
75  * @bits: the size of the mux value in bits
84  * struct ingenic_cgu_div_info - information about a divider
91  * @bits: the size of the divide value in bits
92  * @ce_bit: the index of the change enable bit within reg, or -1 if there
94  * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
95  * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
113  * struct ingenic_cgu_fixdiv_info - information about a fixed divider
121  * struct ingenic_cgu_gate_info - information about a clock gate
123  * @bit: offset of the bit in the register that controls the gate
125  * @delay_us: delay in microseconds after which the clock is considered stable
135  * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
143  * struct ingenic_cgu_clk_info - information about a clock
148  *           within the clock_info array of the CGU, or -1 in entries
150  * @pll: information valid if type includes CGU_CLK_PLL
177 		struct ingenic_cgu_pll_info pll;  member
191  * struct ingenic_cgu - data about the CGU
209  * struct ingenic_clk - private data for a clock
210  * @hw: see Documentation/driver-api/clk.rst
212  * @idx: the index of this clock in cgu->clock_info
223  * ingenic_cgu_new() - create a new CGU instance
226  * @num_clocks: the number of entries in clock_info
237  * ingenic_cgu_register_clocks() - Registers the clocks
242  * Return: 0 on success or -errno if unsuccesful.