i915/display/intel_dpll_mgr.h

2  * Copyright © 2012-2016 Intel Corporation
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34 	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
48  * enum intel_dpll_id - possible DPLL ids
54 	 * @DPLL_ID_PRIVATE: non-shared dpll in use
56 	DPLL_ID_PRIVATE = -1,
59 	 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
63 	 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
125 	 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
129 	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
130 	 *                      TGL TC PLL 1 port 1 (TC1)
134 	 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
135 	 *                      TGL TC PLL 1 port 2 (TC2)
139 	 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
140 	 *                      TGL TC PLL 1 port 3 (TC3)
144 	 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
145 	 *                      TGL TC PLL 1 port 4 (TC4)
149 	 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
153 	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
198 	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
233 	u32 clock; /* in KHz */
245 	u32 clock; /* in KHz */
248 	u8 pll[20];  member
252 	u32 clock; /* in kHz */
284  * struct intel_shared_dpll_state - hold the DPLL atomic state
287  * either its current state (in struct &intel_shared_dpll) or a desired
288  * future state which would be applied by an atomic mode set (stored in
300 	 * @hw_state: hardware configuration for the DPLL stored in
307  * struct dpll_info - display PLL platform specific info
334 	 * not in use by any CRTC.
342 	 * (for TC->TBT fallback).
348  * struct intel_shared_dpll - display PLL with tracked state and users
354 	 * Store the state for the pll, including its hw state
370 	 * @on: is the PLL actually active? Disabled during modeset
380 	 * @wakeref: In some platforms a device-level runtime pm reference may
396 			struct intel_shared_dpll *pll,
409 					const struct intel_shared_dpll *pll,
417 			const struct intel_shared_dpll *pll,
420 			     struct intel_shared_dpll *pll,