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/linux-6.12.1/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
26 #define MDIO_MMD_POWER_UNIT 13 /* PHY Power Unit */
41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
50 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
52 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
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/linux-6.12.1/Documentation/devicetree/bindings/net/pcs/
Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
19 general it can be used to communicate with any compatible PHY.
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
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/linux-6.12.1/rust/kernel/net/phy/
Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! PHY register interfaces.
7 //! This module provides support for accessing PHY registers in the
21 /// Accesses PHY registers.
24 /// C22 and C45 PHY registers.
32 /// // read C45 PMA/PMD control 1 register
37 /// dev.genphy_read_status::<phy::C22>();
40 /// dev.genphy_read_status::<phy::C45>();
44 /// Reads a PHY register.
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - google,gs101-ufs-phy
19 - samsung,exynos7-ufs-phy
20 - samsung,exynosautov9-ufs-phy
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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Dcdns,dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pratyush Yadav <pratyush@kernel.org>
15 - cdns,dphy
16 - ti,j721e-dphy
23 - description: PMA state machine clock
24 - description: PLL reference clock
26 clock-names:
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Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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/linux-6.12.1/drivers/net/phy/
Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
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Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
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Ddp83tg720.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TG720 PHY
9 #include <linux/phy.h>
73 * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY.
76 * This sequence is based on the documented procedure for the DP83TG720 PHY.
84 /* Initialize the PHY to run the TDR test as described in the in dp83tg720_cable_test_start()
85 * "DP83TG720S-Q1: Configuring for Open Alliance Specification in dp83tg720_cable_test_start()
132 * dp83tg720_cable_test_get_status - Get the status of the cable test for the
133 * DP83TG720 PHY.
192 /* Autoneg is not supported and this PHY supports only one speed. in dp83tg720_config_aneg()
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Dmarvell-88x2222.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
11 #include <linux/phy.h>
36 /* 1000Base-X/SGMII Control Register */
39 /* 1000BASE-X/SGMII Status Register */
42 /* 1000Base-X Auto-Negotiation Advertisement Register */
45 /* 1000Base-X PHY Specific Status Register */
60 /* SFI PMA transmit enable */
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/linux-6.12.1/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
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Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/linux-6.12.1/drivers/net/pcs/
Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
13 #include <linux/phy.h>
17 #include "pcs-xpcs.h"
169 const struct dw_xpcs_compat *compat = &desc->compat[i]; in xpcs_find_compat()
171 for (j = 0; j < compat->num_interfaces; j++) in xpcs_find_compat()
172 if (compat->interface[j] == interface) in xpcs_find_compat()
183 compat = xpcs_find_compat(xpcs->desc, interface); in xpcs_get_an_mode()
185 return -ENODEV; in xpcs_get_an_mode()
187 return compat->an_mode; in xpcs_get_an_mode()
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/linux-6.12.1/drivers/phy/cadence/
Dphy-cadence-sierra.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence Sierra PHY Driver
10 #include <linux/clk-provider.h>
15 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy.h>
24 #include <dt-bindings/phy/phy-cadence.h>
29 /* PHY register offsets */
204 /* PHY PCS common registers */
210 /* PHY PCS lane registers */
217 /* PHY PMA common registers */
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Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
20 #include <linux/phy/phy.h>
62 * register offsets from DPTX PHY register block base (i.e MHDP
77 * register offsets from SD0801 PHY register block base (i.e MHDP
168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
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/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
64 struct phy *phy; member
76 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
78 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
83 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
86 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
89 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
24 The AUX and PMA registers are not part of this range, they are instead
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/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
19 #include <linux/phy/phy.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
27 /* Exynos USB PHY registers */
37 /* Exynos5: USB 3.0 DRD PHY registers */
116 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
135 /* Exynos850: USB DRD PHY registers */
149 * On versions without SS ports (like E850), bit 3 is for the 2.0 phy (HS),
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Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-pmu.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
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/linux-6.12.1/include/linux/pcs/
Dpcs-xpcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy.h>
48 u32 pma; member
/linux-6.12.1/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
158 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
206 /* Transmit inter-frame gap adjustment value */
222 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
240 /* In-Band FCS enable (FCS not stripped) */
256 /* In-Band FCS enable (FCS not generated) */
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/linux-6.12.1/drivers/net/phy/aquantia/
Daquantia_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Aquantia PHY
14 #include <linux/phy.h>
88 /* Sleep and timeout for checking if the Processor-Intensive
111 int len_l = min(stat->size, 16); in aqr107_get_stat()
112 int len_h = stat->size - len_l; in aqr107_get_stat()
116 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); in aqr107_get_stat()
120 ret = val & GENMASK(len_l - 1, 0); in aqr107_get_stat()
122 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); in aqr107_get_stat()
126 ret += (val & GENMASK(len_h - 1, 0)) << 16; in aqr107_get_stat()
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/linux-6.12.1/drivers/net/phy/qcom/
Dqca808x.c1 // SPDX-License-Identifier: GPL-2.0+
3 #include <linux/phy.h>
60 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
70 #define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
73 #define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
90 MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
150 return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || in qca808x_is_prefer_master()
151 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); in qca808x_is_prefer_master()
156 return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); in qca808x_has_fast_retrain_or_slave_seed()
172 unsigned long *possible = phydev->possible_interfaces; in qca808x_fill_possible_interfaces()
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