Lines Matching +full:phy +full:- +full:pma
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
26 #define MDIO_MMD_POWER_UNIT 13 /* PHY Power Unit */
41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
50 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
52 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
64 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
65 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
66 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
67 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
68 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
69 #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
70 #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
71 #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
72 #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
73 #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
74 #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
75 #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
76 #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
77 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
78 #define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */
79 #define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */
80 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
81 #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
82 #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
83 #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */
84 #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */
85 #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
86 #define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */
87 #define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */
117 /* 10PASS-TS/2BASE-TL */
125 #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
137 #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
138 #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
144 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
163 #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
164 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
165 #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
166 #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
167 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
168 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
169 #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
170 #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
171 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
172 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
173 #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
174 #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
175 #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
176 #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
177 #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
178 #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
179 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
182 #define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */
184 #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
185 #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
186 #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
187 #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
194 #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
195 #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
196 #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
197 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
198 #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
199 #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
200 #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
201 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
206 #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
207 #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
208 #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
227 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
228 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
229 #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
230 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
231 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
232 #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
233 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
234 #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
235 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
236 #define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
237 #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
263 /* PHY XGXS lane state register. */
270 /* PMA 10GBASE-T pair swap & polarity */
278 /* PMA 10GBASE-T TX power register. */
279 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
281 /* PMA 10GBASE-T SNR registers. */
282 /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
286 /* PMA 10GBASE-R FEC ability register. */
290 /* PMA 10GBASE-R Fast Retrain status and control register. */
293 /* PCS 10GBASE-R/-T status register 1. */
296 /* PCS 10GBASE-R/-T status register 2. */
300 /* AN 10GBASE-T control register. */
301 #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */
302 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
303 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
304 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
306 /* AN 10GBASE-T status register. */
317 /* 10BASE-T1L PMA control */
320 #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 /* Low-power mode */
325 /* 10BASE-T1L PMA status register. */
326 #define MDIO_PMA_10T1L_STAT_LINK 0x0001 /* PMA receive link up */
330 #define MDIO_PMA_10T1L_STAT_EEE 0x0400 /* PHY has EEE ability */
331 #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */
332 #define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 /* PHY has 2.4 Vpp operating mode ability */
333 #define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */
335 /* 10BASE-T1L PCS control register. */
339 /* BASE-T1 PMA/PMD extended ability register. */
340 #define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 /* 100BASE-T1 Ability */
341 #define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */
342 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */
344 /* BASE-T1 auto-negotiation advertisement register [15:0] */
352 /* BASE-T1 auto-negotiation advertisement register [31:16] */
353 #define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
354 #define MDIO_AN_T1_ADV_M_1000BT1 0x0080 /* advertise 1000BASE-T1 */
355 #define MDIO_AN_T1_ADV_M_100BT1 0x0020 /* advertise 100BASE-T1 */
358 /* BASE-T1 auto-negotiation advertisement register [47:32] */
359 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
360 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
362 /* BASE-T1 AN LP Base Page ability register [15:0] */
370 /* BASE-T1 AN LP Base Page ability register [31:16] */
372 #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
374 /* BASE-T1 AN LP Base Page ability register [47:32] */
375 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
376 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
378 /* 10BASE-T1 AN control register */
379 #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */
381 /* 10BASE-T1 AN status register */
382 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */
384 /* BASE-T1 PMA/PMD control register */
386 #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */
387 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */
389 /* 1000BASE-T1 PCS control register */
391 #define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 /* Global PMA transmit disable */
394 /* 1000BASE-T1 PCS status register */
407 /* Note: the two defines above can be potentially used by the user-land
426 /* AN MultiGBASE-T AN control 2 */
434 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
436 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
441 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
443 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
466 /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
473 #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
474 #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
476 #define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */
477 #define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */
479 #define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */
480 #define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */
482 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
483 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */
485 #define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */
486 #define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */
488 #define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */
489 #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */
490 #define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */