Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
125 /* Vendor-specific BIST registers */
142 #define TXC_BIST_CTRL_TYPE_TSR 3 /* TranSwitch pseudo-random */
147 /* Stop BIST (self-clears when stop complete) */
162 /* The PHY sometimes needs a reset to bring the link back up. So long as
182 /* Reset the PMA/PMD MMD. The documentation is explicit that this does a
200 netif_err(efx, hw, efx->net_dev, TXCNAME ": reset timed out!\n"); in txc_reset_phy()
211 /* Set PMA to test into loopback using Mt Diablo reg as per app note */ in txc_bist_one()
241 non-zero */ in txc_bist_one()
245 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. " in txc_bist_one()
247 rc = -EIO; in txc_bist_one()
251 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. " in txc_bist_one()
253 rc = -EIO; in txc_bist_one()
258 netif_info(efx, hw, efx->net_dev, TXCNAME": BIST pass\n"); in txc_bist_one()
275 /* Push the non-configurable defaults into the PHY. This must be
282 * (PHY<->MAC) as this is believed less likely to upset Falcon in txc_apply_defaults()
298 * PHY rev.s */ in txc_apply_defaults()
318 falcon_board(efx)->type->init_phy(efx); in txc_apply_defaults()
325 /* Allocate phy private storage */ in txc43128_phy_probe()
328 return -ENOMEM; in txc43128_phy_probe()
329 efx->phy_data = phy_data; in txc43128_phy_probe()
330 phy_data->phy_mode = efx->phy_mode; in txc43128_phy_probe()
332 efx->mdio.mmds = TXC_REQUIRED_DEVS; in txc43128_phy_probe()
333 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; in txc43128_phy_probe()
335 efx->loopback_modes = TXC_LOOPBACKS | FALCON_XMAC_LOOPBACKS; in txc43128_phy_probe()
340 /* Initialisation entry point for this PHY driver */
364 if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) in txc_glrgs_lane_power()
382 if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) { in txc_analog_lane_power()
398 !!(efx->phy_mode & PHY_MODE_LOW_POWER), in txc_set_power()
401 /* Global register bank is in PCS, PHY XS. These control the host in txc_set_power()
406 /* Analog register bank in PMA/PMD, PHY XS */ in txc_set_power()
418 while (--tries) { in txc_reset_logic_mmd()
425 netif_info(efx, hw, efx->net_dev, in txc_reset_logic_mmd()
434 * PCS or the PHYXS and the result is a reset of both host- and in txc_reset_logic()
435 * line-side logic. */ in txc_reset_logic()
446 struct txc43128_data *phy_data = efx->phy_data; in txc43128_phy_reconfigure()
447 enum ef4_phy_mode mode_change = efx->phy_mode ^ phy_data->phy_mode; in txc43128_phy_reconfigure()
450 if (efx->phy_mode & mode_change & PHY_MODE_TX_DISABLED) { in txc43128_phy_reconfigure()
469 phy_data->phy_mode = efx->phy_mode; in txc43128_phy_reconfigure()
470 phy_data->loopback_mode = efx->loopback_mode; in txc43128_phy_reconfigure()
483 kfree(efx->phy_data); in txc43128_phy_remove()
484 efx->phy_data = NULL; in txc43128_phy_remove()
491 struct txc43128_data *data = efx->phy_data; in txc43128_phy_poll()
492 bool was_up = efx->link_state.up; in txc43128_phy_poll()
494 efx->link_state.up = txc43128_phy_read_link(efx); in txc43128_phy_poll()
495 efx->link_state.speed = 10000; in txc43128_phy_poll()
496 efx->link_state.fd = true; in txc43128_phy_poll()
497 efx->link_state.fc = efx->wanted_fc; in txc43128_phy_poll()
499 if (efx->link_state.up || (efx->loopback_mode != LOOPBACK_NONE)) { in txc43128_phy_poll()
500 data->bug10934_timer = jiffies; in txc43128_phy_poll()
502 if (time_after_eq(jiffies, (data->bug10934_timer + in txc43128_phy_poll()
504 data->bug10934_timer = jiffies; in txc43128_phy_poll()
509 return efx->link_state.up != was_up; in txc43128_phy_poll()
536 results[0] = rc ? -1 : 1; in txc43128_run_tests()
543 mdio45_ethtool_ksettings_get(&efx->mdio, cmd); in txc43128_get_link_ksettings()