Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
64 struct phy *phy; member
76 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
78 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
83 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
86 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
89 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
90 return -EINVAL; in rockchip_p3phy_set_mode()
98 struct phy *phy = priv->phy; in rockchip_p3phy_rk3568_init() local
103 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3568_init()
104 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); in rockchip_p3phy_rk3568_init()
106 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3568_init()
107 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); in rockchip_p3phy_rk3568_init()
108 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3568_init()
114 dev_info(&phy->dev, "bifurcation enabled\n"); in rockchip_p3phy_rk3568_init()
115 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
117 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, in rockchip_p3phy_rk3568_init()
120 dev_dbg(&phy->dev, "bifurcation disabled\n"); in rockchip_p3phy_rk3568_init()
121 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
125 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3568_init()
127 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3568_init()
132 dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3568_init()
147 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1, in rockchip_p3phy_rk3588_init()
148 priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN : in rockchip_p3phy_rk3588_init()
150 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1, in rockchip_p3phy_rk3588_init()
151 priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN : in rockchip_p3phy_rk3588_init()
153 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1, in rockchip_p3phy_rk3588_init()
154 priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN : in rockchip_p3phy_rk3588_init()
156 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1, in rockchip_p3phy_rk3588_init()
157 priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN : in rockchip_p3phy_rk3588_init()
160 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3588_init()
161 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); in rockchip_p3phy_rk3588_init()
164 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3588_init()
165 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3588_init()
167 if (priv->lanes[i] == 3) in rockchip_p3phy_rk3588_init()
169 if (priv->lanes[i] == 4) in rockchip_p3phy_rk3588_init()
174 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, in rockchip_p3phy_rk3588_init()
178 if (!IS_ERR(priv->pipe_grf)) { in rockchip_p3phy_rk3588_init()
181 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, in rockchip_p3phy_rk3588_init()
185 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3588_init()
187 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
191 ret |= regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
196 dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3588_init()
205 static int rockchip_p3phy_init(struct phy *phy) in rockchip_p3phy_init() argument
207 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_init()
210 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_p3phy_init()
212 dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); in rockchip_p3phy_init()
216 reset_control_assert(priv->p30phy); in rockchip_p3phy_init()
219 if (priv->ops->phy_init) { in rockchip_p3phy_init()
220 ret = priv->ops->phy_init(priv); in rockchip_p3phy_init()
222 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_p3phy_init()
228 static int rockchip_p3phy_exit(struct phy *phy) in rockchip_p3phy_exit() argument
230 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_exit()
232 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_p3phy_exit()
233 reset_control_assert(priv->p30phy); in rockchip_p3phy_exit()
247 struct device *dev = &pdev->dev; in rockchip_p3phy_probe()
249 struct device_node *np = dev->of_node; in rockchip_p3phy_probe()
254 return -ENOMEM; in rockchip_p3phy_probe()
256 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in rockchip_p3phy_probe()
257 if (IS_ERR(priv->mmio)) { in rockchip_p3phy_probe()
258 ret = PTR_ERR(priv->mmio); in rockchip_p3phy_probe()
262 priv->ops = of_device_get_match_data(&pdev->dev); in rockchip_p3phy_probe()
263 if (!priv->ops) { in rockchip_p3phy_probe()
265 return -EINVAL; in rockchip_p3phy_probe()
268 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); in rockchip_p3phy_probe()
269 if (IS_ERR(priv->phy_grf)) { in rockchip_p3phy_probe()
271 return PTR_ERR(priv->phy_grf); in rockchip_p3phy_probe()
274 if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) { in rockchip_p3phy_probe()
275 priv->pipe_grf = in rockchip_p3phy_probe()
276 syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_p3phy_probe()
277 "rockchip,pipe-grf"); in rockchip_p3phy_probe()
278 if (IS_ERR(priv->pipe_grf)) in rockchip_p3phy_probe()
281 priv->pipe_grf = NULL; in rockchip_p3phy_probe()
284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
285 priv->lanes, 2, in rockchip_p3phy_probe()
286 ARRAY_SIZE(priv->lanes)); in rockchip_p3phy_probe()
288 /* if no data-lanes assume aggregation */ in rockchip_p3phy_probe()
289 if (priv->num_lanes == -EINVAL) { in rockchip_p3phy_probe()
290 dev_dbg(dev, "no data-lanes property found\n"); in rockchip_p3phy_probe()
291 priv->num_lanes = 1; in rockchip_p3phy_probe()
292 priv->lanes[0] = 1; in rockchip_p3phy_probe()
293 } else if (priv->num_lanes < 0) { in rockchip_p3phy_probe()
294 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); in rockchip_p3phy_probe()
295 return priv->num_lanes; in rockchip_p3phy_probe()
298 ret = of_property_read_variable_u32_array(dev->of_node, in rockchip_p3phy_probe()
299 "rockchip,rx-common-refclk-mode", in rockchip_p3phy_probe()
300 priv->rx_cmn_refclk_mode, 1, in rockchip_p3phy_probe()
301 ARRAY_SIZE(priv->rx_cmn_refclk_mode)); in rockchip_p3phy_probe()
303 * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in in rockchip_p3phy_probe()
306 if (ret == -EINVAL) { in rockchip_p3phy_probe()
307 for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++) in rockchip_p3phy_probe()
308 priv->rx_cmn_refclk_mode[i] = 1; in rockchip_p3phy_probe()
310 dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n", in rockchip_p3phy_probe()
315 priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); in rockchip_p3phy_probe()
316 if (IS_ERR(priv->phy)) { in rockchip_p3phy_probe()
318 return PTR_ERR(priv->phy); in rockchip_p3phy_probe()
321 priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); in rockchip_p3phy_probe()
322 if (IS_ERR(priv->p30phy)) { in rockchip_p3phy_probe()
323 return dev_err_probe(dev, PTR_ERR(priv->p30phy), in rockchip_p3phy_probe()
324 "failed to get phy reset control\n"); in rockchip_p3phy_probe()
326 if (!priv->p30phy) in rockchip_p3phy_probe()
327 dev_info(dev, "no phy reset control specified\n"); in rockchip_p3phy_probe()
329 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_p3phy_probe()
330 if (priv->num_clks < 1) in rockchip_p3phy_probe()
331 return -ENODEV; in rockchip_p3phy_probe()
334 phy_set_drvdata(priv->phy, priv); in rockchip_p3phy_probe()
340 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
341 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
349 .name = "rockchip-snps-pcie3-phy",
354 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");