Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
54 return -EOPNOTSUPP; in genphy_c45_pma_resume()
62 * genphy_c45_pma_suspend - suspends the PMA module
68 return -EOPNOTSUPP; in genphy_c45_pma_suspend()
76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
84 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
97 return -EOPNOTSUPP; in genphy_c45_pma_baset1_setup_master_slave()
106 * genphy_c45_pma_setup_forced - configures a forced speed
114 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
115 return -EINVAL; in genphy_c45_pma_setup_forced()
127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
128 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
132 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
145 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
150 /* Assume 2.5Gbase-T */ in genphy_c45_pma_setup_forced()
155 /* Assume 5Gbase-T */ in genphy_c45_pma_setup_forced()
160 /* Assume 10Gbase-T */ in genphy_c45_pma_setup_forced()
164 return -EINVAL; in genphy_c45_pma_setup_forced()
181 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
195 * The preference is set in the BIT(4) of BASE-T1 AN
197 * is forced or not, it is set in the BIT(12) of BASE-T1
199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
214 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
234 return -EOPNOTSUPP; in genphy_c45_baset1_an_config_aneg()
237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
259 * genphy_c45_an_config_aneg - configure advertisement registers
262 * Configure advertisement registers based on modes set in phydev->advertising
272 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
273 phydev->supported); in genphy_c45_an_config_aneg()
284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
311 * genphy_c45_an_disable_aneg - disable auto-negotiation
314 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
315 * are controlled through the PMA/PMD MMD registers.
332 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
335 * This assumes that the auto-negotiation MMD is present.
337 * Enable and restart auto-negotiation.
352 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
356 * This assumes that the auto-negotiation MMD is present.
358 * Check, and restart auto-negotiation if needed.
386 * genphy_c45_aneg_done - return auto-negotiation complete status
389 * This assumes that the auto-negotiation MMD is present.
391 * Reads the status register from the auto-negotiation MMD, returning:
392 * - positive if auto-negotiation is complete
393 * - negative errno code on error
394 * - zero otherwise
411 * genphy_c45_read_link - read the overall link status from the MMDs
415 * that the link is up, set phydev->link to 1. If an error is encountered,
424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
433 phydev->link = 0; in genphy_c45_read_link()
443 * drops can be detected. Do not double-read the status in genphy_c45_read_link()
447 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
463 phydev->link = link; in genphy_c45_read_link()
469 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
470 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
487 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
488 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
513 * genphy_c45_read_lpa - read the link partner advertisement and pause
518 * in @phydev. This assumes that the auto-negotiation MMD is present, and
519 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
535 phydev->lp_advertising); in genphy_c45_read_lpa()
536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
538 phydev->pause = 0; in genphy_c45_read_lpa()
539 phydev->asym_pause = 0; in genphy_c45_read_lpa()
544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
568 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
596 * genphy_c45_read_pma - read link speed etc from PMA
603 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
611 phydev->speed = SPEED_10; in genphy_c45_read_pma()
614 phydev->speed = SPEED_100; in genphy_c45_read_pma()
617 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
620 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
623 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
626 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
629 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
633 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
646 * genphy_c45_read_mdix - read mdix status from PMA
653 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
661 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
665 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
669 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
679 * genphy_c45_write_eee_adv - write advertised EEE link modes
687 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
693 val &= ~phydev->eee_broken_modes; in genphy_c45_write_eee_adv()
695 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_write_eee_adv()
710 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_write_eee_adv()
713 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 in genphy_c45_write_eee_adv()
727 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
729 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_write_eee_adv()
746 * genphy_c45_read_eee_adv - read advertised EEE link modes
754 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
755 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_read_eee_adv()
765 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_adv()
766 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 in genphy_c45_read_eee_adv()
777 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
778 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_read_eee_adv()
792 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
801 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
802 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 in genphy_c45_read_eee_lpa()
812 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_lpa()
813 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 in genphy_c45_read_eee_lpa()
824 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
825 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register in genphy_c45_read_eee_lpa()
839 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
846 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 in genphy_c45_read_eee_cap1()
854 * read as 0. Also, it seems unlikely anybody will build a PHY which in genphy_c45_read_eee_cap1()
855 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. in genphy_c45_read_eee_cap1()
861 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
866 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
867 phydev->supported); in genphy_c45_read_eee_cap1()
873 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21
880 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 in genphy_c45_read_eee_cap2()
887 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ in genphy_c45_read_eee_cap2()
891 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap2()
897 * genphy_c45_read_eee_abilities - read supported EEE link modes
908 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
915 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_abilities()
922 phydev->supported)) { in genphy_c45_read_eee_abilities()
923 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register in genphy_c45_read_eee_abilities()
931 phydev->supported_eee, in genphy_c45_read_eee_abilities()
940 * genphy_c45_an_config_eee_aneg - configure EEE advertisement
945 if (!phydev->eee_enabled) { in genphy_c45_an_config_eee_aneg()
951 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
955 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
958 * Read the supported link modes from the extended BASE-T1 ability register
969 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
973 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
977 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
985 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
993 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA
996 * Read the supported link modes from the PMA/PMD extended ability register
1008 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1011 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1014 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1017 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1020 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1023 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1027 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1030 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1034 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1037 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1047 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1051 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1066 * genphy_c45_pma_read_abilities - read supported link modes from PMA
1069 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
1071 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
1073 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
1080 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
1081 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
1088 phydev->supported); in genphy_c45_pma_read_abilities()
1096 phydev->supported, in genphy_c45_pma_read_abilities()
1100 phydev->supported, in genphy_c45_pma_read_abilities()
1104 phydev->supported, in genphy_c45_pma_read_abilities()
1123 * The preference is read from the BIT(4) of BASE-T1 AN
1125 * is forced or not, it is read from BASE-T1 AN advertisement
1133 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1134 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1148 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1153 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1161 * genphy_c45_read_status - read PHY status
1164 * Reads status from PHY and sets phy_device members accordingly.
1174 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1175 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1176 phydev->pause = 0; in genphy_c45_read_status()
1177 phydev->asym_pause = 0; in genphy_c45_read_status()
1179 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1200 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1203 * Description: If auto-negotiation is enabled, we configure the
1204 * advertising, and then restart auto-negotiation. If it is not
1212 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1242 * genphy_c45_fast_retrain - configure fast retrain registers
1246 * Description: If fast-retrain is enabled, we configure PHY as
1259 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1277 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1281 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1295 return -ENODEV; in genphy_c45_plca_get_cfg()
1297 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; in genphy_c45_plca_get_cfg()
1303 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); in genphy_c45_plca_get_cfg()
1309 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; in genphy_c45_plca_get_cfg()
1310 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); in genphy_c45_plca_get_cfg()
1316 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; in genphy_c45_plca_get_cfg()
1322 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; in genphy_c45_plca_get_cfg()
1323 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); in genphy_c45_plca_get_cfg()
1330 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1332 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1335 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1345 // PLCA IDVER is read-only in genphy_c45_plca_set_cfg()
1346 if (plca_cfg->version >= 0) in genphy_c45_plca_set_cfg()
1347 return -EINVAL; in genphy_c45_plca_set_cfg()
1350 if (plca_cfg->enabled == 0) { in genphy_c45_plca_set_cfg()
1360 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { in genphy_c45_plca_set_cfg()
1361 /* if one between node count and node ID is -not- to be in genphy_c45_plca_set_cfg()
1365 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { in genphy_c45_plca_set_cfg()
1375 if (plca_cfg->node_cnt >= 0) in genphy_c45_plca_set_cfg()
1377 (plca_cfg->node_cnt << 8); in genphy_c45_plca_set_cfg()
1379 if (plca_cfg->node_id >= 0) in genphy_c45_plca_set_cfg()
1381 (plca_cfg->node_id); in genphy_c45_plca_set_cfg()
1390 if (plca_cfg->to_tmr >= 0) { in genphy_c45_plca_set_cfg()
1393 plca_cfg->to_tmr); in genphy_c45_plca_set_cfg()
1400 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { in genphy_c45_plca_set_cfg()
1401 /* if one between burst count and burst timer is -not- to be in genphy_c45_plca_set_cfg()
1405 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { in genphy_c45_plca_set_cfg()
1415 if (plca_cfg->burst_cnt >= 0) in genphy_c45_plca_set_cfg()
1417 (plca_cfg->burst_cnt << 8); in genphy_c45_plca_set_cfg()
1419 if (plca_cfg->burst_tmr >= 0) in genphy_c45_plca_set_cfg()
1421 (plca_cfg->burst_tmr); in genphy_c45_plca_set_cfg()
1431 if (plca_cfg->enabled > 0) { in genphy_c45_plca_set_cfg()
1445 * genphy_c45_plca_get_status - get PLCA status from standard registers
1449 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1462 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); in genphy_c45_plca_get_status()
1468 * genphy_c45_eee_is_active - get EEE status
1474 * Description: this function will read local and link partner PHY
1497 eee_active = phy_check_valid(phydev->speed, phydev->duplex, in genphy_c45_eee_is_active()
1514 * genphy_c45_ethtool_get_eee - get EEE supported and status
1533 data->eee_enabled = is_enabled; in genphy_c45_ethtool_get_eee()
1534 data->eee_active = ret; in genphy_c45_ethtool_get_eee()
1535 linkmode_copy(data->supported, phydev->supported_eee); in genphy_c45_ethtool_get_eee()
1536 linkmode_copy(data->advertised, adv); in genphy_c45_ethtool_get_eee()
1537 linkmode_copy(data->lp_advertised, lp); in genphy_c45_ethtool_get_eee()
1544 * genphy_c45_ethtool_set_eee - set EEE supported and status
1552 * non-destructive way.
1554 * value if there was a change which triggered auto-neg.
1561 if (data->eee_enabled) { in genphy_c45_ethtool_set_eee()
1562 unsigned long *adv = data->advertised; in genphy_c45_ethtool_set_eee()
1567 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { in genphy_c45_ethtool_set_eee()
1569 return -EINVAL; in genphy_c45_ethtool_set_eee()
1572 adv = phydev->supported_eee; in genphy_c45_ethtool_set_eee()
1575 linkmode_copy(phydev->advertising_eee, adv); in genphy_c45_ethtool_set_eee()
1578 phydev->eee_enabled = data->eee_enabled; in genphy_c45_ethtool_set_eee()
1599 .name = "Generic Clause 45 PHY",