pcie\-host\-1 (full) in projects: linux-6.12.1

Searched +full:pcie +full:- +full:host +full:- +full:1 (Results 1 – 25 of 748) sorted by relevance

/linux-6.12.1/drivers/pci/controller/
D	pcie-rcar-host.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 16 #include <linux/clk-provider.h> 34 #include "pcie-rcar.h" 45 /* Structure representing the PCIe interface */ 47 struct rcar_pcie pcie; member [all …]`
D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 7 tristate "Aardvark PCIe controller" 13 Add support for Aardvark 64bit PCIe Host Controller. This 18 tristate "Altera PCIe controller" 21 Say Y here if you want to enable PCIe controller support on Altera 25 tristate "Altera PCIe MSI feature" 29 Say Y here if you want PCIe MSI support for the Altera FPGA. 38 tristate "Apple PCIe controller" 44 Say Y here if you want to enable PCIe controller support on Apple 45 system-on-chips, like the Apple M1. This is required for the USB [all …]
D	pcie-mt7621.c	`1 // SPDX-License-Identifier: GPL-2.0+ 12 * support RT2880/RT3883 PCIe 15 * support RT6855/MT7620 PCIe 35 /* MediaTek-specific configuration registers / 40 / Host-PCI bridge registers / 48 / PCIe RC control registers / 67 struct mt7621_pcie_port - PCIe port information 70 * @pcie: pointer to PCIe host info 81 struct mt7621_pcie pcie; member 91 struct mt7621_pcie - PCIe host information [all …]`
D	pcie-mediatek.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * MediaTek PCIe host controller driver. 32 /* PCIe shared registers / 38 / PCIe per port registers / 44 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 69 / PCIe V2 share registers / 72 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) 8) 74 /* PCIe V2 per-port registers / 97 Define PCIe to AHB window size as 2^33 to support max 8GB address space 103 /* PCIe V2 configuration transaction header */ [all …]`
D	pcie-mediatek-gen3.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * MediaTek PCIe host controller driver. 11 #include <linux/clk-provider.h> 53 #define PCIE_PHY_RSTB BIT(1) 71 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) 75 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) 79 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) 101 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) 113 (((((size) - 1) << 1) & GENMASK(6, 1)) \| PCIE_ATR_EN) 116 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) [all …]`
D	pcie-rcar.c	1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 12 #include "pcie-rcar.h" 14 void rcar_pci_write_reg(struct rcar_pcie pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument 16 writel(val, pcie->base + reg); in rcar_pci_write_reg() 19 u32 rcar_pci_read_reg(struct rcar_pcie pcie, unsigned int reg) in rcar_pci_read_reg() argument 21 return readl(pcie->base + reg); in rcar_pci_read_reg() 24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument 27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32() [all …]
D	pcie-iproc.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> 9 #include <linux/pci-ecam.h> 17 #include <linux/irqchip/arm-gic-v3.h> 24 #include "pcie-iproc.h" 28 #define EP_MODE_SURVIVE_PERST_SHIFT 1 43 #define CFG_ADDR_CFG_TYPE_1 1 56 #define CFG_RD_UR 1 73 #define OARR_SIZE_CFG_SHIFT 1 91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific [all …]`
/linux-6.12.1/Documentation/devicetree/bindings/clock/
D	mvebu-gated-clock.txt	`12 ----------------------------------- 14 1 pex0_en PCIe 0 Clock out 15 2 pex1_en PCIe 1 Clock out 16 3 ge1 Gigabit Ethernet 1 18 5 pex0 PCIe Cntrl 0 19 9 pex1 PCIe Cntrl 1 20 15 sata0 SATA Host 0 21 17 sdio SDHCI Host 25 30 sata1 SATA Host 0 29 ----------------------------------- [all …]`
/linux-6.12.1/Documentation/devicetree/bindings/pci/
D	ti,j721e-pci-host.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI J721E PCI Host (PCIe Wrapper) 11 - Kishon Vijay Abraham I <kishon@ti.com> 16 - const: ti,j721e-pcie-host 17 - const: ti,j784s4-pcie-host 18 - description: PCIe controller in AM64 [all …]`
D	host-generic-pci.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic PCI host controller 10 - Will Deacon <will@kernel.org> 13 Firmware-initialised PCI host controllers and PCI emulations, such as the 14 virtio-pci implementations found in kvmtool and other para-virtualised 21 Configuration Space is assumed to be memory-mapped (as opposed to being 26 For CAM, this 24-bit offset is: [all …]
D	ti-pci.txt	3 PCIe DesignWare Controller 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated) 5 Should be "ti,dra7-pcie-ep" for EP (deprecated) 6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode 7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode 8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode 9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode 10 - phys : list of PHY specifiers (used by generic PHY framework) 11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", [all …]
D	apple,pcie.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Apple PCIe host controller 10 - Mark Kettenis <kettenis@openbsd.org> 13 The Apple PCIe host controller is a PCIe host controller with 16 The controller incorporates Synopsys DesigWare PCIe logic to 18 PCIe host bridges is absent. 22 the standard "reset-gpios" and "max-link-speed" properties appear on [all …]
D	pcie-al.txt	`1 * Amazon Annapurna Labs PCIe host bridge 3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare 5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 7 Properties of the host controller node that differ from it are: 9 - compatible: 13 - "amazon,al-alpine-v2-pcie" for alpine_v2 14 - "amazon,al-alpine-v3-pcie" for alpine_v3 16 - reg: 18 Value type: <prop-encoded-array> 19 Definition: Register ranges as listed in the reg-names property [all …]`
D	rcar-pci-host.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas R-Car PCIe Host 11 - Marek Vasut <marek.vasut+renesas@gmail.com> 12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 - $ref: /schemas/pci/pci-host-bridge.yaml# 20 - const: renesas,pcie-r8a7779 # R-Car H1 21 - items: [all …]`
D	mediatek,mt7621-pcie.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek MT7621 PCIe controller 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) 14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link 16 MT7621 PCIe HOST Topology 18 .-------. [all …]`
D	ti,am65-pci-host.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI AM65 PCI Host 11 - Kishon Vijay Abraham I <kishon@ti.com> 14 - $ref: /schemas/pci/pci-host-bridge.yaml# 19 - ti,am654-pcie-rc 20 - ti,keystone-pcie [all …]`
D	xlnx,axi-pcie-host.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx AXI PCIe Root Port Bridge 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 17 const: xlnx,axi-pcie-host-1.00.a 20 maxItems: 1 23 maxItems: 1 [all …]`
D	brcm,stb-pcie.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Brcmstb PCIe Host Controller 10 - Jim Quinlan <james.quinlan@broadcom.com> 15 - enum: 16 - brcm,bcm2711-pcie # The Raspberry Pi 4 17 - brcm,bcm4908-pcie 18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4 [all …]`
D	plda,xpressrich3-axi-common.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PLDA XpressRICH PCIe host common properties 10 - Daire McNamara <daire.mcnamara@microchip.com> 11 - Kevin Xie <kevin.xie@starfivetech.com> 14 Generic PLDA XpressRICH PCIe host common properties. 17 - $ref: /schemas/pci/pci-host-bridge.yaml# 23 reg-names: [all …]`
D	pci.txt	3 PCI Bus Binding to: IEEE Std 1275-1994 4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf 9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf 11 Additionally to the properties specified in the above standards a host bridge 14 - linux,pci-domain: 15 If present this property assigns a fixed PCI domain number to a host bridge, 18 host bridges in the system, otherwise potentially conflicting domain numbers 19 may be assigned to root buses behind different host bridges. The domain 20 number for each host bridge in the system must be unique. 21 - max-link-speed: [all …]
D	amlogic,axg-pcie.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Amlogic Meson AXG DWC PCIe SoC controller 10 - Neil Armstrong <neil.armstrong@linaro.org> 13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 16 - $ref: /schemas/pci/pci-host-bridge.yaml# 17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 19 # We need a select here so we don't match all nodes with 'snps,dw-pcie' [all …]
/linux-6.12.1/Documentation/admin-guide/
D	thunderbolt.rst	1 .. SPDX-License-Identifier: GPL-2.0 8 manager is an entity running on the host router (host controller) 19 ``user`` which means PCIe tunneling is disabled by default. The 25 ----------------------------------- 27 should be a userspace tool that handles all the low-level details, keeps 31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``. 35 ``/etc/udev/rules.d/99-local.rules``:: 37 ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", ATTR{authorized}="1" 46 be DMA masters and thus read contents of the host memory without CPU and OS 50 Some USB4 systems have a BIOS setting to disable PCIe tunneling. This is [all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
D	nvidia,tegra210-xusb-padctl.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
D	nvidia,tegra124-xusb-padctl.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
/linux-6.12.1/Documentation/misc-devices/
D	spear-pcie-gadget.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 Spear PCIe Gadget Driver 24 PCIe gadget support for SPEAr13XX platform 29 Its main purpose is to configure selected dual mode PCIe controller as device 31 type. This driver can be used to show spear's PCIe device capability. 37 ----------------------- 42 no_of_msi zero if MSI is not enabled by host. A positive value is the 53 ------------------------ 61 inta write 1 to assert INTA and 0 to de-assert. 78 Program all PCIe registers in such a way that when this device is connected [all …]

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