Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
32 /* PCIe shared registers */
38 /* PCIe per port registers */
44 #define PCIE_PORT_PERST(x) BIT(1 + (x))
69 /* PCIe V2 share registers */
72 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
74 /* PCIe V2 per-port registers */
97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
103 /* PCIe V2 configuration transaction header */
125 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
134 #define PCIE_PIPE_SRSTB BIT(1)
145 * struct mtk_pcie_soc - differentiate between host generations
146 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
147 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
149 * @device_id: device ID which this host need to be fixed
165 * struct mtk_pcie_port - PCIe port information
168 * @pcie: pointer to PCIe host info
190 struct mtk_pcie *pcie; member
209 * struct mtk_pcie - PCIe host information
210 * @dev: pointer to PCIe device
212 * @cfg: IO mapped register map for PCIe config
213 * @free_ck: free-run reference clock
214 * @ports: pointer to PCIe port information
215 * @soc: pointer to SoC-dependent operations
227 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) in mtk_pcie_subsys_powerdown() argument
229 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
231 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_subsys_powerdown()
239 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_port_free() local
240 struct device *dev = pcie->dev; in mtk_pcie_port_free()
242 devm_iounmap(dev, port->base); in mtk_pcie_port_free()
243 list_del(&port->list); in mtk_pcie_port_free()
247 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) in mtk_pcie_put_resources() argument
251 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_put_resources()
252 phy_power_off(port->phy); in mtk_pcie_put_resources()
253 phy_exit(port->phy); in mtk_pcie_put_resources()
254 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_put_resources()
255 clk_disable_unprepare(port->obff_ck); in mtk_pcie_put_resources()
256 clk_disable_unprepare(port->axi_ck); in mtk_pcie_put_resources()
257 clk_disable_unprepare(port->aux_ck); in mtk_pcie_put_resources()
258 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_put_resources()
259 clk_disable_unprepare(port->sys_ck); in mtk_pcie_put_resources()
263 mtk_pcie_subsys_powerdown(pcie); in mtk_pcie_put_resources()
271 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, in mtk_pcie_check_cfg_cpld()
277 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) in mtk_pcie_check_cfg_cpld()
288 /* Write PCIe configuration transaction header for Cfgrd */ in mtk_pcie_hw_rd_cfg()
290 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_rd_cfg()
291 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_rd_cfg()
293 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_rd_cfg()
296 tmp = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
298 writel(tmp, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
305 *val = readl(port->base + PCIE_CFG_RDATA); in mtk_pcie_hw_rd_cfg()
307 if (size == 1) in mtk_pcie_hw_rd_cfg()
318 /* Write PCIe configuration transaction header for Cfgwr */ in mtk_pcie_hw_wr_cfg()
320 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_wr_cfg()
321 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_wr_cfg()
323 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_wr_cfg()
327 writel(val, port->base + PCIE_CFG_WDATA); in mtk_pcie_hw_wr_cfg()
330 val = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
332 writel(val, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
341 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_find_port() local
349 while (bus && bus->number) { in mtk_pcie_find_port()
350 dev = bus->self; in mtk_pcie_find_port()
351 bus = dev->bus; in mtk_pcie_find_port()
352 devfn = dev->devfn; in mtk_pcie_find_port()
355 list_for_each_entry(port, &pcie->ports, list) in mtk_pcie_find_port()
356 if (port->slot == PCI_SLOT(devfn)) in mtk_pcie_find_port()
366 u32 bn = bus->number; in mtk_pcie_config_read()
379 u32 bn = bus->number; in mtk_pcie_config_write()
398 /* MT2712/MT7622 only support 32-bit MSI addresses */ in mtk_compose_msi_msg()
399 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_compose_msi_msg()
400 msg->address_hi = 0; in mtk_compose_msi_msg()
401 msg->address_lo = lower_32_bits(addr); in mtk_compose_msi_msg()
403 msg->data = data->hwirq; in mtk_compose_msi_msg()
405 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", in mtk_compose_msi_msg()
406 (int)data->hwirq, msg->address_hi, msg->address_lo); in mtk_compose_msi_msg()
412 u32 hwirq = data->hwirq; in mtk_msi_ack_irq()
414 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); in mtk_msi_ack_irq()
426 struct mtk_pcie_port *port = domain->host_data; in mtk_pcie_irq_domain_alloc()
429 WARN_ON(nr_irqs != 1); in mtk_pcie_irq_domain_alloc()
430 mutex_lock(&port->lock); in mtk_pcie_irq_domain_alloc()
432 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); in mtk_pcie_irq_domain_alloc()
434 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
435 return -ENOSPC; in mtk_pcie_irq_domain_alloc()
438 __set_bit(bit, port->msi_irq_in_use); in mtk_pcie_irq_domain_alloc()
440 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
443 domain->host_data, handle_edge_irq, in mtk_pcie_irq_domain_alloc()
455 mutex_lock(&port->lock); in mtk_pcie_irq_domain_free()
457 if (!test_bit(d->hwirq, port->msi_irq_in_use)) in mtk_pcie_irq_domain_free()
458 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", in mtk_pcie_irq_domain_free()
459 d->hwirq); in mtk_pcie_irq_domain_free()
461 __clear_bit(d->hwirq, port->msi_irq_in_use); in mtk_pcie_irq_domain_free()
463 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_free()
474 .name = "MTK PCIe MSI",
488 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); in mtk_pcie_allocate_msi_domains()
490 mutex_init(&port->lock); in mtk_pcie_allocate_msi_domains()
492 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, in mtk_pcie_allocate_msi_domains()
494 if (!port->inner_domain) { in mtk_pcie_allocate_msi_domains()
495 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); in mtk_pcie_allocate_msi_domains()
496 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
499 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, in mtk_pcie_allocate_msi_domains()
500 port->inner_domain); in mtk_pcie_allocate_msi_domains()
501 if (!port->msi_domain) { in mtk_pcie_allocate_msi_domains()
502 dev_err(port->pcie->dev, "failed to create MSI domain\n"); in mtk_pcie_allocate_msi_domains()
503 irq_domain_remove(port->inner_domain); in mtk_pcie_allocate_msi_domains()
504 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
515 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_pcie_enable_msi()
517 writel(val, port->base + PCIE_IMSI_ADDR); in mtk_pcie_enable_msi()
519 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
521 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
524 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) in mtk_pcie_irq_teardown() argument
528 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_irq_teardown()
529 irq_set_chained_handler_and_data(port->irq, NULL, NULL); in mtk_pcie_irq_teardown()
531 if (port->irq_domain) in mtk_pcie_irq_teardown()
532 irq_domain_remove(port->irq_domain); in mtk_pcie_irq_teardown()
535 if (port->msi_domain) in mtk_pcie_irq_teardown()
536 irq_domain_remove(port->msi_domain); in mtk_pcie_irq_teardown()
537 if (port->inner_domain) in mtk_pcie_irq_teardown()
538 irq_domain_remove(port->inner_domain); in mtk_pcie_irq_teardown()
541 irq_dispose_mapping(port->irq); in mtk_pcie_irq_teardown()
549 irq_set_chip_data(irq, domain->host_data); in mtk_pcie_intx_map()
561 struct device *dev = port->pcie->dev; in mtk_pcie_init_irq_domain()
568 dev_err(dev, "no PCIe Intc node found\n"); in mtk_pcie_init_irq_domain()
569 return -ENODEV; in mtk_pcie_init_irq_domain()
572 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, in mtk_pcie_init_irq_domain()
575 if (!port->irq_domain) { in mtk_pcie_init_irq_domain()
577 return -ENODEV; in mtk_pcie_init_irq_domain()
598 status = readl(port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
602 writel(1 << bit, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
603 generic_handle_domain_irq(port->irq_domain, in mtk_pcie_intr_handler()
604 bit - INTX_SHIFT); in mtk_pcie_intr_handler()
615 * edge-triggered interrupt type, its status should in mtk_pcie_intr_handler()
619 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
620 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { in mtk_pcie_intr_handler()
622 generic_handle_domain_irq(port->inner_domain, bit); in mtk_pcie_intr_handler()
633 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_setup_irq() local
634 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
640 dev_err(dev, "failed to init PCIe IRQ domain\n"); in mtk_pcie_setup_irq()
644 if (of_property_present(dev->of_node, "interrupt-names")) in mtk_pcie_setup_irq()
645 port->irq = platform_get_irq_byname(pdev, "pcie_irq"); in mtk_pcie_setup_irq()
647 port->irq = platform_get_irq(pdev, port->slot); in mtk_pcie_setup_irq()
649 if (port->irq < 0) in mtk_pcie_setup_irq()
650 return port->irq; in mtk_pcie_setup_irq()
652 irq_set_chained_handler_and_data(port->irq, in mtk_pcie_setup_irq()
660 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port_v2() local
661 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_startup_port_v2() local
664 const struct mtk_pcie_soc *soc = port->pcie->soc; in mtk_pcie_startup_port_v2()
668 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); in mtk_pcie_startup_port_v2()
670 mem = entry->res; in mtk_pcie_startup_port_v2()
672 return -EINVAL; in mtk_pcie_startup_port_v2()
674 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ in mtk_pcie_startup_port_v2()
675 if (pcie->base) { in mtk_pcie_startup_port_v2()
676 val = readl(pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
677 val |= PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
678 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
679 writel(val, pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
680 } else if (pcie->cfg) { in mtk_pcie_startup_port_v2()
681 val = PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
682 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
683 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); in mtk_pcie_startup_port_v2()
687 writel(0, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
690 * Enable PCIe link down reset, if link status changed from link up to in mtk_pcie_startup_port_v2()
694 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
697 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and in mtk_pcie_startup_port_v2()
698 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should in mtk_pcie_startup_port_v2()
703 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ in mtk_pcie_startup_port_v2()
704 val = readl(port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
707 writel(val, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
710 if (soc->need_fix_class_id) { in mtk_pcie_startup_port_v2()
712 writew(val, port->base + PCIE_CONF_VEND_ID); in mtk_pcie_startup_port_v2()
715 writew(val, port->base + PCIE_CONF_CLASS_ID); in mtk_pcie_startup_port_v2()
718 if (soc->need_fix_device_id) in mtk_pcie_startup_port_v2()
719 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); in mtk_pcie_startup_port_v2()
722 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, in mtk_pcie_startup_port_v2()
726 return -ETIMEDOUT; in mtk_pcie_startup_port_v2()
729 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
731 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
736 /* Set AHB to PCIe translation windows */ in mtk_pcie_startup_port_v2()
737 val = lower_32_bits(mem->start) | in mtk_pcie_startup_port_v2()
739 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); in mtk_pcie_startup_port_v2()
741 val = upper_32_bits(mem->start); in mtk_pcie_startup_port_v2()
742 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); in mtk_pcie_startup_port_v2()
744 /* Set PCIe to AXI translation memory space.*/ in mtk_pcie_startup_port_v2()
746 writel(val, port->base + PCIE_AXI_WINDOW0); in mtk_pcie_startup_port_v2()
754 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
757 bus->number), pcie->base + PCIE_CFG_ADDR); in mtk_pcie_map_bus()
759 return pcie->base + PCIE_CFG_DATA + (where & 3); in mtk_pcie_map_bus()
770 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port() local
771 u32 func = PCI_FUNC(port->slot); in mtk_pcie_startup_port()
772 u32 slot = PCI_SLOT(port->slot << 3); in mtk_pcie_startup_port()
777 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
778 val |= PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
779 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
781 /* de-assert port PERST_N */ in mtk_pcie_startup_port()
782 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
783 val &= ~PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
784 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
787 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, in mtk_pcie_startup_port()
791 return -ETIMEDOUT; in mtk_pcie_startup_port()
794 val = readl(pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
795 val |= PCIE_PORT_INT_EN(port->slot); in mtk_pcie_startup_port()
796 writel(val, pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
800 port->base + PCIE_BAR0_SETUP); in mtk_pcie_startup_port()
803 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); in mtk_pcie_startup_port()
807 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
808 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
812 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
813 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
817 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
818 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
822 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
823 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
830 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_enable_port() local
831 struct device *dev = pcie->dev; in mtk_pcie_enable_port()
834 err = clk_prepare_enable(port->sys_ck); in mtk_pcie_enable_port()
836 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); in mtk_pcie_enable_port()
840 err = clk_prepare_enable(port->ahb_ck); in mtk_pcie_enable_port()
842 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); in mtk_pcie_enable_port()
846 err = clk_prepare_enable(port->aux_ck); in mtk_pcie_enable_port()
848 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); in mtk_pcie_enable_port()
852 err = clk_prepare_enable(port->axi_ck); in mtk_pcie_enable_port()
854 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); in mtk_pcie_enable_port()
858 err = clk_prepare_enable(port->obff_ck); in mtk_pcie_enable_port()
860 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); in mtk_pcie_enable_port()
864 err = clk_prepare_enable(port->pipe_ck); in mtk_pcie_enable_port()
866 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); in mtk_pcie_enable_port()
870 reset_control_assert(port->reset); in mtk_pcie_enable_port()
871 reset_control_deassert(port->reset); in mtk_pcie_enable_port()
873 err = phy_init(port->phy); in mtk_pcie_enable_port()
875 dev_err(dev, "failed to initialize port%d phy\n", port->slot); in mtk_pcie_enable_port()
879 err = phy_power_on(port->phy); in mtk_pcie_enable_port()
881 dev_err(dev, "failed to power on port%d phy\n", port->slot); in mtk_pcie_enable_port()
885 if (!pcie->soc->startup(port)) in mtk_pcie_enable_port()
888 dev_info(dev, "Port%d link down\n", port->slot); in mtk_pcie_enable_port()
890 phy_power_off(port->phy); in mtk_pcie_enable_port()
892 phy_exit(port->phy); in mtk_pcie_enable_port()
894 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_enable_port()
896 clk_disable_unprepare(port->obff_ck); in mtk_pcie_enable_port()
898 clk_disable_unprepare(port->axi_ck); in mtk_pcie_enable_port()
900 clk_disable_unprepare(port->aux_ck); in mtk_pcie_enable_port()
902 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_enable_port()
904 clk_disable_unprepare(port->sys_ck); in mtk_pcie_enable_port()
909 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, in mtk_pcie_parse_port() argument
914 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
921 return -ENOMEM; in mtk_pcie_parse_port()
924 port->base = devm_platform_ioremap_resource_byname(pdev, name); in mtk_pcie_parse_port()
925 if (IS_ERR(port->base)) { in mtk_pcie_parse_port()
927 return PTR_ERR(port->base); in mtk_pcie_parse_port()
931 port->sys_ck = devm_clk_get(dev, name); in mtk_pcie_parse_port()
932 if (IS_ERR(port->sys_ck)) { in mtk_pcie_parse_port()
934 return PTR_ERR(port->sys_ck); in mtk_pcie_parse_port()
939 port->ahb_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
940 if (IS_ERR(port->ahb_ck)) in mtk_pcie_parse_port()
941 return PTR_ERR(port->ahb_ck); in mtk_pcie_parse_port()
944 port->axi_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
945 if (IS_ERR(port->axi_ck)) in mtk_pcie_parse_port()
946 return PTR_ERR(port->axi_ck); in mtk_pcie_parse_port()
949 port->aux_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
950 if (IS_ERR(port->aux_ck)) in mtk_pcie_parse_port()
951 return PTR_ERR(port->aux_ck); in mtk_pcie_parse_port()
954 port->obff_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
955 if (IS_ERR(port->obff_ck)) in mtk_pcie_parse_port()
956 return PTR_ERR(port->obff_ck); in mtk_pcie_parse_port()
959 port->pipe_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
960 if (IS_ERR(port->pipe_ck)) in mtk_pcie_parse_port()
961 return PTR_ERR(port->pipe_ck); in mtk_pcie_parse_port()
963 snprintf(name, sizeof(name), "pcie-rst%d", slot); in mtk_pcie_parse_port()
964 port->reset = devm_reset_control_get_optional_exclusive(dev, name); in mtk_pcie_parse_port()
965 if (PTR_ERR(port->reset) == -EPROBE_DEFER) in mtk_pcie_parse_port()
966 return PTR_ERR(port->reset); in mtk_pcie_parse_port()
969 snprintf(name, sizeof(name), "pcie-phy%d", slot); in mtk_pcie_parse_port()
970 port->phy = devm_phy_optional_get(dev, name); in mtk_pcie_parse_port()
971 if (IS_ERR(port->phy)) in mtk_pcie_parse_port()
972 return PTR_ERR(port->phy); in mtk_pcie_parse_port()
974 port->slot = slot; in mtk_pcie_parse_port()
975 port->pcie = pcie; in mtk_pcie_parse_port()
977 if (pcie->soc->setup_irq) { in mtk_pcie_parse_port()
978 err = pcie->soc->setup_irq(port, node); in mtk_pcie_parse_port()
983 INIT_LIST_HEAD(&port->list); in mtk_pcie_parse_port()
984 list_add_tail(&port->list, &pcie->ports); in mtk_pcie_parse_port()
989 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) in mtk_pcie_subsys_powerup() argument
991 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerup()
1000 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_subsys_powerup()
1001 if (IS_ERR(pcie->base)) in mtk_pcie_subsys_powerup()
1002 return PTR_ERR(pcie->base); in mtk_pcie_subsys_powerup()
1006 "mediatek,generic-pciecfg"); in mtk_pcie_subsys_powerup()
1008 pcie->cfg = syscon_node_to_regmap(cfg_node); in mtk_pcie_subsys_powerup()
1010 if (IS_ERR(pcie->cfg)) in mtk_pcie_subsys_powerup()
1011 return PTR_ERR(pcie->cfg); in mtk_pcie_subsys_powerup()
1014 pcie->free_ck = devm_clk_get(dev, "free_ck"); in mtk_pcie_subsys_powerup()
1015 if (IS_ERR(pcie->free_ck)) { in mtk_pcie_subsys_powerup()
1016 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) in mtk_pcie_subsys_powerup()
1017 return -EPROBE_DEFER; in mtk_pcie_subsys_powerup()
1019 pcie->free_ck = NULL; in mtk_pcie_subsys_powerup()
1026 err = clk_prepare_enable(pcie->free_ck); in mtk_pcie_subsys_powerup()
1041 static int mtk_pcie_setup(struct mtk_pcie *pcie) in mtk_pcie_setup() argument
1043 struct device *dev = pcie->dev; in mtk_pcie_setup()
1044 struct device_node *node = dev->of_node, *child; in mtk_pcie_setup()
1048 slot = of_get_pci_domain_nr(dev->of_node); in mtk_pcie_setup()
1059 err = mtk_pcie_parse_port(pcie, child, slot); in mtk_pcie_setup()
1064 err = mtk_pcie_parse_port(pcie, node, slot); in mtk_pcie_setup()
1069 err = mtk_pcie_subsys_powerup(pcie); in mtk_pcie_setup()
1074 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_setup()
1077 /* power down PCIe subsys if slots are all empty (link down) */ in mtk_pcie_setup()
1078 if (list_empty(&pcie->ports)) in mtk_pcie_setup()
1079 mtk_pcie_subsys_powerdown(pcie); in mtk_pcie_setup()
1089 struct device *dev = &pdev->dev; in mtk_pcie_probe()
1090 struct mtk_pcie *pcie; in mtk_pcie_probe() local
1091 struct pci_host_bridge *host; in mtk_pcie_probe() local
1094 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in mtk_pcie_probe()
1095 if (!host) in mtk_pcie_probe()
1096 return -ENOMEM; in mtk_pcie_probe()
1098 pcie = pci_host_bridge_priv(host); in mtk_pcie_probe()
1100 pcie->dev = dev; in mtk_pcie_probe()
1101 pcie->soc = of_device_get_match_data(dev); in mtk_pcie_probe()
1102 platform_set_drvdata(pdev, pcie); in mtk_pcie_probe()
1103 INIT_LIST_HEAD(&pcie->ports); in mtk_pcie_probe()
1105 err = mtk_pcie_setup(pcie); in mtk_pcie_probe()
1109 host->ops = pcie->soc->ops; in mtk_pcie_probe()
1110 host->sysdata = pcie; in mtk_pcie_probe()
1111 host->msi_domain = pcie->soc->no_msi; in mtk_pcie_probe()
1113 err = pci_host_probe(host); in mtk_pcie_probe()
1120 if (!list_empty(&pcie->ports)) in mtk_pcie_probe()
1121 mtk_pcie_put_resources(pcie); in mtk_pcie_probe()
1127 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) in mtk_pcie_free_resources() argument
1129 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_free_resources() local
1130 struct list_head *windows = &host->windows; in mtk_pcie_free_resources()
1137 struct mtk_pcie *pcie = platform_get_drvdata(pdev); in mtk_pcie_remove() local
1138 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_remove() local
1140 pci_stop_root_bus(host->bus); in mtk_pcie_remove()
1141 pci_remove_root_bus(host->bus); in mtk_pcie_remove()
1142 mtk_pcie_free_resources(pcie); in mtk_pcie_remove()
1144 mtk_pcie_irq_teardown(pcie); in mtk_pcie_remove()
1146 mtk_pcie_put_resources(pcie); in mtk_pcie_remove()
1151 struct mtk_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_suspend_noirq() local
1154 if (list_empty(&pcie->ports)) in mtk_pcie_suspend_noirq()
1157 list_for_each_entry(port, &pcie->ports, list) { in mtk_pcie_suspend_noirq()
1158 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_suspend_noirq()
1159 clk_disable_unprepare(port->obff_ck); in mtk_pcie_suspend_noirq()
1160 clk_disable_unprepare(port->axi_ck); in mtk_pcie_suspend_noirq()
1161 clk_disable_unprepare(port->aux_ck); in mtk_pcie_suspend_noirq()
1162 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_suspend_noirq()
1163 clk_disable_unprepare(port->sys_ck); in mtk_pcie_suspend_noirq()
1164 phy_power_off(port->phy); in mtk_pcie_suspend_noirq()
1165 phy_exit(port->phy); in mtk_pcie_suspend_noirq()
1168 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_suspend_noirq()
1175 struct mtk_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_resume_noirq() local
1178 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1181 clk_prepare_enable(pcie->free_ck); in mtk_pcie_resume_noirq()
1183 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_resume_noirq()
1187 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1188 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_resume_noirq()
1227 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1228 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1229 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1230 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1231 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1240 .name = "mtk-pcie",
1247 MODULE_DESCRIPTION("MediaTek PCIe host controller driver");