bindings/clock/mvebu-gated-clock.txt

12 -----------------------------------
14 1	pex0_en	PCIe 0 Clock out
15 2	pex1_en	PCIe 1 Clock out
16 3	ge1	Gigabit Ethernet 1
18 5	pex0	PCIe Cntrl 0
19 9	pex1	PCIe Cntrl 1
20 15	sata0	SATA Host 0
21 17	sdio	SDHCI Host
25 30	sata1	SATA Host 0
29 -----------------------------------
33 5	pex0		PCIe 0 Clock out
34 6	pex1		PCIe 1 Clock out
39 16	usb3		USB3 Host
40 17	sdio		SDHCI Host
41 18	usb		USB Host
43 20	sata1_link	SATA 1 Link
44 21	sata1_core	SATA 1 Core
51 30	crypto1_enc	Cryptographic Unit Port 1 Encryption
52 31	crypto1_core	Cryptographic Unit Port 1 Core
56 -----------------------------------
59 3	ge1		Gigabit Ethernet 1
61 5	pex1		PCIe 1
62 6	pex2		PCIe 2
63 7	pex3		PCIe 3
64 8	pex0		PCIe 0
65 9	usb3h0		USB3 Host 0
66 10	usb3h1		USB3 Host 1
71 16	crypto1z	Cryptographic 1 Z
74 21	crypto1		Cryptographic 1
78 28	xor1		XOR 1
79 30	sata1		SATA 1
83 -----------------------------------
84 5	pex1		PCIe 1
85 6	pex2		PCIe 2
86 7	pex3		PCIe 3
87 8	pex0		PCIe 0
88 9	usb3h0		USB3 Host 0
89 10	usb3h1		USB3 Host 1
93 28	xor1		XOR 1
97 -----------------------------------
99 1	ge3	Gigabit Ethernet 3
101 3	ge1	Gigabit Ethernet 1
103 5	pex0	PCIe Cntrl 0
104 6	pex1	PCIe Cntrl 1
105 7	pex2	PCIe Cntrl 2
106 8	pex3	PCIe Cntrl 3
109 15	sata0	SATA Host 0
111 17	sdio	SDHCI Host
112 18	usb0	USB Host 0
113 19	usb1	USB Host 1
114 20	usb2	USB Host 2
118 28	xor1	XOR DMA 1
120 30	sata1	SATA Host 1
124 -----------------------------------
125 3	ge1	Gigabit Ethernet 1
127 5	pex0	PCIe Cntrl 0
128 17	sdio	SDHCI Host
129 18	usb0	USB Host 0
134 -----------------------------------
135 0	usb0	USB Host 0
136 1	usb1	USB Host 1
138 3	sata	SATA Host
139 4	pex0	PCIe Cntrl 0
140 5	pex1	PCIe Cntrl 1
141 8	sdio0	SDHCI Host 0
142 9	sdio1	SDHCI Host 1
146 13	i2s1	I2S Cntrl 1
151 24	xor1	XOR DMA 1
157 -----------------------------------
159 2	pex0	PCIe Cntrl 0
160 3	usb0	USB Host 0
167 14	sata0	SATA Host 0
168 15	sata1	SATA Host 1
169 16	xor1	XOR DMA 1
171 18	pex1	PCIe Cntrl 1
172 19	ge1	Gigabit Ethernet 1
176 - compatible : shall be one of the following:
177 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 	"marvell,dove-gating-clock" - for Dove SoC clock gating
184 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 	compatible = "marvell,dove-gating-clock";
198 	#clock-cells = <1>;
202 	compatible = "marvell,dove-sdhci";