bindings/pci/pci.txt

3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
11 Additionally to the properties specified in the above standards a host bridge
14 - linux,pci-domain:
15    If present this property assigns a fixed PCI domain number to a host bridge,
18    host bridges in the system, otherwise potentially conflicting domain numbers
19    may be assigned to root buses behind different host bridges.  The domain
20    number for each host bridge in the system must be unique.
21 - max-link-speed:
22    If present this property specifies PCI gen for link capability.  Host
26    for gen2, and '1' for gen1. Any other values are invalid.
27 - reset-gpios:
28    If present this property specifies PERST# GPIO. Host drivers can parse the
30 - supports-clkreq:
32    root port to downstream device and host bridge drivers can do programming
34    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
36 PCI-PCI Bridge properties
37 -------------------------
39 PCIe root ports and switch ports may be described explicitly in the device
40 tree, as children of the host bridge node. Even though those devices are
42 aren't provided by standard PCIe capabilities.
46 - reg:
47    Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
48    document, it is a five-cell address encoded as (phys.hi phys.mid
56    number of a root port is the first number in the bus-range property,
60    above this port, then phys.hi contains the 8-bit function number as
61    0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
63    OS is ARI-aware.
67 - external-facing:
68    When present, the port is external-facing. All bridges and endpoints
76 pcie@10000000 {
77 	compatible = "pci-host-ecam-generic";
79 	pcie@0008 {
80 		/* Root port 00:01.0 is external-facing */
82 		external-facing;