bindings/pci/xlnx%2Caxi-pcie-host.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI PCIe Root Port Bridge
10   - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13   - $ref: /schemas/pci/pci-host-bridge.yaml#
17     const: xlnx,axi-pcie-host-1.00.a
20     maxItems: 1
23     maxItems: 1
27       - description: |
31   "#interrupt-cells":
32     const: 1
34   interrupt-controller:
38       interrupt-controller: true
40       "#address-cells":
43       "#interrupt-cells":
44         const: 1
47       - interrupt-controller
48       - "#address-cells"
49       - "#interrupt-cells"
54   - compatible
55   - reg
56   - ranges
57   - interrupts
58   - interrupt-map
59   - "#interrupt-cells"
60   - interrupt-controller
65   - |
66     #include <dt-bindings/interrupt-controller/arm-gic.h>
67     #include <dt-bindings/interrupt-controller/irq.h>
69     pcie@50000000 {
70         compatible = "xlnx,axi-pcie-host-1.00.a";
72         #address-cells = <3>;
73         #size-cells = <2>;
74         #interrupt-cells = <1>;
77         interrupt-map-mask = <0 0 0 7>;
78         interrupt-map = <0 0 0 1 &pcie_intc 1>,
83         pcie_intc: interrupt-controller {
84             interrupt-controller;
85             #address-cells = <0>;
86             #interrupt-cells = <1>;