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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
Dcache.json105Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
Dmetrics.json89 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
145 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
152 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
Dmetrics.json14 …"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((…
60 …"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)…
100 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
142level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
Dmetrics.json4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC…
15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp…
61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) -
101 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
115 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
122 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
129level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
136 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
143level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
Dcache.json111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
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/linux-6.12.1/arch/x86/kvm/mmu/
Dtdp_iter.c1 // SPDX-License-Identifier: GPL-2.0
9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
16 iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep); in tdp_iter_refresh_sptep()
25 iter->yielded = false; in tdp_iter_restart()
26 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_restart()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
32 iter->valid = true; in tdp_iter_restart()
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Dtdp_mmu.c1 // SPDX-License-Identifier: GPL-2.0
17 INIT_LIST_HEAD(&kvm->arch.tdp_mmu_roots); in kvm_mmu_init_tdp_mmu()
18 spin_lock_init(&kvm->arch.tdp_mmu_pages_lock); in kvm_mmu_init_tdp_mmu()
26 lockdep_assert_held_read(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
28 lockdep_assert_held_write(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
43 WARN_ON(atomic64_read(&kvm->arch.tdp_mmu_pages)); in kvm_mmu_uninit_tdp_mmu()
44 WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots)); in kvm_mmu_uninit_tdp_mmu()
48 * can run before the VM is torn down. Putting the last reference to in kvm_mmu_uninit_tdp_mmu()
56 free_page((unsigned long)sp->spt); in tdp_mmu_free_sp()
78 if (!refcount_dec_and_test(&root->tdp_mmu_root_count)) in kvm_tdp_mmu_put_root()
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/linux-6.12.1/kernel/rcu/
Dtree.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
39 * Definition for node within the RCU grace-period-detection hierarchy.
45 unsigned long gp_seq; /* Track rsp->gp_seq. */
56 /* Per-GP initial value for qsmask. */
57 /* Initialized from ->qsmaskinitnext at the */
64 /* Per-GP initial values for expmask. */
65 /* Initialized from ->expmaskinitnext at the */
79 int grplo; /* lowest-numbered CPU here. */
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/linux-6.12.1/Documentation/admin-guide/mm/
Dnumaperf.rst21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
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/linux-6.12.1/drivers/net/wireless/ath/ath5k/
Dani.c33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
63 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
70 * and ath9k use only the last two levels, making this in ath5k_ani_set_noise_immunity_level()
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
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/linux-6.12.1/Documentation/arch/arm/
Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_pt_walk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * DOC: GPU page-table tree walking.
9 * The utilities in this file are similar to the CPU page-table walk
11 * the various levels of a page-table tree with an unsigned integer rather
12 * than by name. 0 is the lowest level, and page-tables with level 0 can
14 * can. The user of the utilities determines the highest level.
17 * Each struct xe_ptw, regardless of level is referred to as a page table, and
20 * levels. A shared page table for a given address range is a page-table which
24 * Please keep this code generic so that it can used as a drm-wide page-
27 static u64 xe_pt_addr_end(u64 addr, u64 end, unsigned int level, in xe_pt_addr_end() argument
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Dxe_pt.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence-array.h>
29 /** @children: Array of page-table child nodes */
34 #define xe_pt_set_addr(__xe_pt, __addr) ((__xe_pt)->addr = (__addr))
35 #define xe_pt_addr(__xe_pt) ((__xe_pt)->addr)
44 #define XE_PT_HIGHEST_LEVEL (ARRAY_SIZE(xe_normal_pt_shifts) - 1)
53 return container_of(pt_dir->children[index], struct xe_pt, base); in xe_pt_entry()
57 unsigned int level) in __xe_pt_empty_pte() argument
60 u16 pat_index = xe->pat.idx[XE_CACHE_WB]; in __xe_pt_empty_pte()
61 u8 id = tile->id; in __xe_pt_empty_pte()
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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/
Dcommon-and-microarch.json9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
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/linux-6.12.1/tools/perf/Documentation/
Ditrace.txt10 of aux-output (refer to perf record)
15 f synthesize first level cache events
16 m synthesize last level cache events
22 l synthesize last branch entries (use with i or x)
23 L synthesize last branch entries on existing event records
27 Z prefer to ignore timestamps (so-called "timeless" decoding)
30 The default is all events i.e. the same as --itrace=iybxwpe,
31 except for perf script where it is --itrace=ce
45 Also the number of last branch entries (default 64, max. 1024) for
50 large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
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/linux-6.12.1/drivers/md/bcache/
Dbtree.c1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
100 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
104 #define insert_lock(s, b) ((b)->level <= (s)->lock)
109 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
115 if (b->level && b->keys.nsets) in bch_btree_init_next()
116 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
118 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
120 if (b->written < btree_blocks(b)) in bch_btree_init_next()
121 bch_bset_init_next(&b->keys, write_block(b), in bch_btree_init_next()
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/linux-6.12.1/drivers/staging/vc04_services/bcm2835-camera/
Dbcm2835-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
81 /* H264 level */
83 /* JPEG Q-factor */
92 /* Sequence number of last buffer */
102 /* last frame completion */
120 #define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ argument
122 v4l2_dbg(level, debug, dev, \
125 (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
126 (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
127 (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
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/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z14/
Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Las…
31 "Unit": "CPU-M-CF",
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/linux-6.12.1/drivers/usb/serial/
Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
73 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
74 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
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/linux-6.12.1/drivers/cpufreq/
Damd-pstate.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * AMD P-state INTERFACE *
29 * struct amd_cpudata - private CPU data for AMD P-State
38 * @nominal_perf: the maximum sustained performance level of the processor,
40 * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
42 * @lowest_perf: the absolute lowest performance level of the processor
45 * @min_limit_perf: Cached value of the performance corresponding to policy->min
46 * @max_limit_perf: Cached value of the performance corresponding to policy->max
47 * @min_limit_freq: Cached value of policy->min (in khz)
48 * @max_limit_freq: Cached value of policy->max (in khz)
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/linux-6.12.1/include/uapi/linux/
Dhyperv.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
66 VSS_OP_COUNT /* Number of operations, must be last */
95 * driver accesses. However, FREEZE messages from Hyper-V contain
102 * auto-recovery, it should not receive such messages.
171 * Maximum value size - used for both key names and value data, and includes
182 * Note: This value is used in defining the KVP exchange message - this value
193 * Maximum key size - the registry limit for the length of an entry name
203 * implementing the host/guest protocol. 2) A user level daemon that is
228 * data gathering functionality in a user mode daemon. The user level daemon
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-class-led9 just be turned on for non-zero brightness settings.
23 Documentation/leds/leds-class-multicolor.rst.
30 Writing non-zero to this file while trigger is active changes the
40 Maximum brightness level for this LED, default is 255 (LED_FULL).
49 Last hardware set brightness level for this LED. Some LEDs
57 Reading this file will return the last brightness level set
73 their documentation see `sysfs-class-led-trigger-*`.
/linux-6.12.1/drivers/media/radio/wl128x/
Dfmdrv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Common header for all FM driver sub-modules.
19 #include <media/v4l2-ioctl.h>
20 #include <media/v4l2-common.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ctrls.h>
113 u8 last_blk_idx; /* Last received RDS block */
145 u16 volume; /* Current volume level */
146 u16 rssi_threshold; /* Current RSSI threshold level */
175 * @ pwr_lvl: Power Level of the Transmission from mixer control
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/linux-6.12.1/tools/perf/tests/shell/lib/
Dperf_metric_validation_rules.json67 …ccesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads…
148 "Description": "Sum of TMA level 1 metrics should be 100%",
175 "Description": "Sum of the level 2 children should equal level 1 parent",
198 "Description": "Sum of the level 2 children should equal level 1 parent",
221 "Description": "Sum of the level 2 children should equal level 1 parent",
244 "Description": "Sum of the level 2 children should equal level 1 parent",
285 "Formula": "a-b",
304 "Formula": "a-b",
323 "Formula": "a-b",
/linux-6.12.1/fs/xfs/libxfs/
Dxfs_btree.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
43 __be32 magic = ops->buf_ops->magic[idx]; in xfs_btree_magic()
45 /* Ensure we asked for crc for crc-only magics. */ in xfs_btree_magic()
57 * on x86-64. Yes, gcc-11 fails to inline them, and explicit inlining of these
122 int level, in __xfs_btree_check_lblock_hdr() argument
125 struct xfs_mount *mp = cur->bc_mp; in __xfs_btree_check_lblock_hdr()
128 if (!uuid_equal(&block->bb_u.l.bb_uuid, &mp->m_sb.sb_meta_uuid)) in __xfs_btree_check_lblock_hdr()
130 if (block->bb_u.l.bb_blkno != in __xfs_btree_check_lblock_hdr()
133 if (block->bb_u.l.bb_pad != cpu_to_be32(0)) in __xfs_btree_check_lblock_hdr()
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