arm/neoverse-v1/metrics.json

14 …"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((…
60 …"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)…
100 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
142 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
156 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
163 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
170 …of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This g…
177 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
183         "MetricExpr": "((LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD)",
184 …last level cache read accesses hit in the cache to the total number of last level cache accesses. …
191 …last level cache read accesses missed to the total number of last level cache accesses. This gives…
198 …"BriefDescription": "This metric measures the number of last level cache read accesses missed per …