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/linux-6.12.1/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
37 /* ----------------------------
39 * ----------------------------
47 /* ----------------------------
49 * ----------------------------
68 /* ----------------------------
70 * ----------------------------
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dia_css_stream_public.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
39 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
40 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
71 int linked_isys_stream_id; /** default value is -1, other value means
128 s32 flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
129 int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/
159 stream_config->online = true;
160 stream_config->left_padding = -1;
267 * @param[in] output_padded_width - the output buffer stride.
[all …]
/linux-6.12.1/include/video/
Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
[all …]
/linux-6.12.1/drivers/media/i2c/cx25840/
Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
135 d--; in count_to_clock_divider()
193 * FIFO register pulse width count computations
199 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
212 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
231 * The 2 lsb's of the pulse width timer count are not accessible, hence
[all …]
/linux-6.12.1/sound/soc/meson/
Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
40 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_toddr_dai_prepare() local
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
57 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_toddr_dai_hw_params() local
58 unsigned int type, width; in axg_toddr_dai_hw_params() local
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
[all …]
Daiu-fifo-i2s.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <sound/soc-dai.h>
13 #include "aiu-fifo.h"
50 struct snd_soc_component *component = dai->component; in aiu_fifo_i2s_trigger()
68 struct snd_soc_component *component = dai->component; in aiu_fifo_i2s_prepare()
90 struct snd_soc_component *component = dai->component; in aiu_fifo_i2s_hw_params()
91 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_i2s_hw_params() local
111 dev_err(dai->dev, "Unsupported physical width %u\n", in aiu_fifo_i2s_hw_params()
113 return -EINVAL; in aiu_fifo_i2s_hw_params()
121 val = params_period_bytes(params) / fifo->fifo_block; in aiu_fifo_i2s_hw_params()
[all …]
Daiu-fifo-spdif.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <sound/soc-dai.h>
12 #include "aiu-fifo.h"
60 struct snd_soc_component *component = dai->component; in fifo_spdif_trigger()
79 return -EINVAL; in fifo_spdif_trigger()
88 struct snd_soc_component *component = dai->component; in fifo_spdif_prepare()
110 struct snd_soc_component *component = dai->component; in fifo_spdif_hw_params()
128 dev_err(dai->dev, "Unsupported physical width %u\n", in fifo_spdif_hw_params()
130 return -EINVAL; in fifo_spdif_hw_params()
140 /* Number bytes read by the FIFO between each IRQ */ in fifo_spdif_hw_params()
[all …]
/linux-6.12.1/drivers/media/rc/
Dite-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
11 /* FIFO sizes */
34 /* hw-specific operation function pointers; most of these must be
35 * called while holding the spin lock, except for the TX FIFO length
50 /* read bytes from RX FIFO; return read count */
53 /* enable tx FIFO space available interrupt */
56 /* disable tx FIFO space available interrupt */
59 /* get number of full TX FIFO slots */
62 /* put a byte to the TX FIFO */
[all …]
/linux-6.12.1/drivers/usb/dwc2/
Dparams.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
130 * struct st_i2c_timings - per-Mode tuning parameters
138 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
152 * struct st_i2c_client - client specific data
153 * @addr: 8-bit target addr, including r/w bit
170 * struct st_i2c_dev - private data of the controller
178 * @scl_min_width_us: SCL line minimum pulse width in us
179 * @sda_min_width_us: SDA line minimum pulse width in us
[all …]
/linux-6.12.1/drivers/video/fbdev/riva/
Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/linux-6.12.1/drivers/media/pci/cx23885/
Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
174 d--; in count_to_clock_divider()
232 * FIFO register pulse width count computations
238 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
251 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
267 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_us()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
[all …]
/linux-6.12.1/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma-mapping.h>
69 u16 width, u16 height, u16 out_width, u16 out_height,
74 u16 width, u16 height, u16 out_width, u16 out_height,
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev); in dispc_runtime_get()
535 r = pm_runtime_put_sync(&dispc.pdev->dev); in dispc_runtime_put()
536 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
[all …]
/linux-6.12.1/arch/arm/mach-sa1100/
Djornada720.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/jornada720.c
17 #include <linux/platform_data/sa11x0-serial.h>
26 #include <asm/mach-types.h>
73 {0x0032,0x4F}, // LCD Horizontal Display Width Register
74 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
76 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
79 {0x003A,0x13}, // LCD Vertical Non-Display Period Register
81 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
90 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
[all …]
/linux-6.12.1/arch/mips/boot/dts/realtek/
Drtl83xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
4 #address-cells = <1>;
5 #size-cells = <1>;
13 compatible = "mti,cpu-interrupt-controller";
14 #address-cells = <0>;
15 #interrupt-cells = <1>;
16 interrupt-controller;
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
/linux-6.12.1/drivers/video/fbdev/mb862xx/
Dmb862xxfb_accel.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver acceleration support
25 struct mb862xxfb_par *par = info->par; in mb862xxfb_write_fifo()
33 free--; in mb862xxfb_write_fifo()
50 if (area->sx >= area->dx && area->sy >= area->dy) in mb86290fb_copyarea()
52 else if (area->sx >= area->dx && area->sy <= area->dy) in mb86290fb_copyarea()
54 else if (area->sx <= area->dx && area->sy >= area->dy) in mb86290fb_copyarea()
59 cmd[3] = (area->sy << 16) | area->sx; in mb86290fb_copyarea()
60 cmd[4] = (area->dy << 16) | area->dx; in mb86290fb_copyarea()
61 cmd[5] = (area->height << 16) | area->width; in mb86290fb_copyarea()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux-6.12.1/drivers/gpu/drm/omapdrm/dss/
Ddispc.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
78 /* An unknown HW bug causing the normal FIFO thresholds not to work */
105 u16 width, u16 height, u16 out_width, u16 out_height,
110 u16 width, u16 height, u16 out_width, u16 out_height,
176 /* maps which plane is using a fifo. fifo-id -> plane-id */
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
[all …]
/linux-6.12.1/include/linux/soc/qcom/
Dgeni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
56 * struct geni_se - GENI Serial Engine
268 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
279 * For QUP HW Version >= 3.10 Rx fifo depth support is increased
319 * geni_se_read_proto() - Read the protocol configured for a serial engine
328 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
334 * geni_se_setup_m_cmd() - Setup the primary sequencer
347 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
[all …]
/linux-6.12.1/arch/m68k/include/asm/
DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
/linux-6.12.1/drivers/gpu/drm/stm/
Dltdc.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 u32 bus_width; /* bus width (32 or 64 bits) */
24 bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
31 bool dynamic_zorder; /* dynamic z-order */
33 bool fifo_threshold; /* fifo underrun threshold supported */
50 u32 fifo_err; /* fifo underrun error counter */
51 u32 fifo_warn; /* fifo underrun warning counter */
52 u32 fifo_threshold; /* fifo underrun threshold */

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