Lines Matching +full:fifo +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma-mapping.h>
69 u16 width, u16 height, u16 out_width, u16 out_height,
74 u16 width, u16 height, u16 out_width, u16 out_height,
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev); in dispc_runtime_get()
535 r = pm_runtime_put_sync(&dispc.pdev->dev); in dispc_runtime_put()
536 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
682 /* YUV -> RGB */ in dispc_setup_color_conv_coef()
683 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, in dispc_setup_color_conv_coef()
686 /* RGB -> YUV */ in dispc_setup_color_conv_coef()
687 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, in dispc_setup_color_conv_coef()
693 if (dispc.feat->has_writeback) in dispc_setup_color_conv_coef()
730 static void dispc_ovl_set_input_size(enum omap_plane plane, int width, in dispc_ovl_set_input_size() argument
733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size()
741 static void dispc_ovl_set_output_size(enum omap_plane plane, int width, in dispc_ovl_set_output_size() argument
748 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_output_size()
1021 if (dispc.feat->has_writeback) in dispc_configure_burst_sizes()
1062 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | in dispc_mgr_set_cpr_coef()
1063 FLD_VAL(coefs->rb, 9, 0); in dispc_mgr_set_cpr_coef()
1064 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | in dispc_mgr_set_cpr_coef()
1065 FLD_VAL(coefs->gb, 9, 0); in dispc_mgr_set_cpr_coef()
1066 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | in dispc_mgr_set_cpr_coef()
1067 FLD_VAL(coefs->bb, 9, 0); in dispc_mgr_set_cpr_coef()
1098 static void dispc_mgr_set_size(enum omap_channel channel, u16 width, in dispc_mgr_set_size() argument
1103 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1104 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); in dispc_mgr_set_size()
1112 int fifo; in dispc_init_fifos() local
1121 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_init_fifos()
1122 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); in dispc_init_fifos()
1124 dispc.fifo_size[fifo] = size; in dispc_init_fifos()
1127 * By default fifos are mapped directly to overlays, fifo 0 to in dispc_init_fifos()
1128 * ovl 0, fifo 1 to ovl 1, etc. in dispc_init_fifos()
1130 dispc.fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1134 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo in dispc_init_fifos()
1137 * giving GFX plane a larger fifo. WB but should work fine with a in dispc_init_fifos()
1138 * smaller fifo. in dispc_init_fifos()
1140 if (dispc.feat->gfx_fifo_workaround) { in dispc_init_fifos()
1157 * Setup default fifo thresholds. in dispc_init_fifos()
1170 if (dispc.feat->has_writeback) { in dispc_init_fifos()
1184 int fifo; in dispc_ovl_get_fifo_size() local
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1188 if (dispc.fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1189 size += dispc.fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", in dispc_ovl_set_fifo_threshold()
1228 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && in dispc_ovl_set_fifo_threshold()
1240 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); in dispc_enable_fifomerge()
1250 * buffer_units, and the fifo thresholds must be buffer_unit aligned. in dispc_ovl_compute_fifo_thresholds()
1269 * We use the same low threshold for both fifomerge and non-fifomerge in dispc_ovl_compute_fifo_thresholds()
1271 * combined fifo size in dispc_ovl_compute_fifo_thresholds()
1275 *fifo_low = ovl_fifo_size - burst_size * 2; in dispc_ovl_compute_fifo_thresholds()
1276 *fifo_high = total_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1281 * in the FIFO to form a burst in dispc_ovl_compute_fifo_thresholds()
1286 *fifo_low = ovl_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1287 *fifo_high = total_fifo_size - buf_unit; in dispc_ovl_compute_fifo_thresholds()
1322 * As a work-around, set force MFLAG to always on. in dispc_init_mflag()
1347 if (dispc.feat->has_writeback) { in dispc_init_mflag()
1472 { 0, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1473 { 1, 2, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1474 { -1, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1475 { -1, 2, -1, 2 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1479 { 0, 1, 0, 1 , -3, 4, -1, 4 }, in dispc_ovl_set_accu_uv()
1480 { -1, 4, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1481 { -1, 1, 0, 1 , -1, 4, -3, 4 }, in dispc_ovl_set_accu_uv()
1482 { -3, 4, -3, 4 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1488 { -1, 1, 0, 1, 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1489 { 0, 1, 0, 1, -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1531 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; in dispc_ovl_set_accu_uv()
1532 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; in dispc_ovl_set_accu_uv()
1533 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; in dispc_ovl_set_accu_uv()
1534 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; in dispc_ovl_set_accu_uv()
1586 accu0 -= accu1; in dispc_ovl_set_scaling_common()
1810 return 1 + (pixels - 1) * ps; in pixinc()
1812 return 1 - (-pixels + 1) * ps; in pixinc()
1820 u16 width, u16 height, in calc_vrfb_rotation_offset() argument
1846 width, height); in calc_vrfb_rotation_offset()
1856 * If the pixel format is YUV or UYVY divide the width in calc_vrfb_rotation_offset()
1861 width = width >> 1; in calc_vrfb_rotation_offset()
1872 (y_predecim * screen_width - x_predecim * width) + in calc_vrfb_rotation_offset()
1879 /* If the pixel format is YUV or UYVY divide the width in calc_vrfb_rotation_offset()
1884 width = width >> 1; in calc_vrfb_rotation_offset()
1893 *row_inc = pixinc(1 - in calc_vrfb_rotation_offset()
1894 (y_predecim * screen_width + x_predecim * width) - in calc_vrfb_rotation_offset()
1907 u16 width, u16 height, in calc_dma_rotation_offset() argument
1930 width, height); in calc_dma_rotation_offset()
1932 /* width & height are overlay sizes, convert to fb sizes */ in calc_dma_rotation_offset()
1935 fbw = width; in calc_dma_rotation_offset()
1939 fbh = width; in calc_dma_rotation_offset()
1954 (y_predecim * screen_width - fbw * x_predecim) + in calc_dma_rotation_offset()
1963 *offset1 = screen_width * (fbh - 1) * ps; in calc_dma_rotation_offset()
1968 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + in calc_dma_rotation_offset()
1970 *pix_inc = pixinc(-x_predecim * screen_width, ps); in calc_dma_rotation_offset()
1973 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; in calc_dma_rotation_offset()
1975 *offset0 = *offset1 - field_offset * screen_width * ps; in calc_dma_rotation_offset()
1978 *row_inc = pixinc(-1 - in calc_dma_rotation_offset()
1979 (y_predecim * screen_width - fbw * x_predecim) - in calc_dma_rotation_offset()
1983 *pix_inc = pixinc(-x_predecim, 2 * ps); in calc_dma_rotation_offset()
1985 *pix_inc = pixinc(-x_predecim, ps); in calc_dma_rotation_offset()
1988 *offset1 = (fbw - 1) * ps; in calc_dma_rotation_offset()
1990 *offset0 = *offset1 - field_offset * ps; in calc_dma_rotation_offset()
1993 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - in calc_dma_rotation_offset()
1994 y_predecim - (fieldmode ? 1 : 0), ps); in calc_dma_rotation_offset()
2000 *offset1 = (fbw - 1) * ps; in calc_dma_rotation_offset()
2005 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + in calc_dma_rotation_offset()
2010 *pix_inc = pixinc(-x_predecim, 2 * ps); in calc_dma_rotation_offset()
2012 *pix_inc = pixinc(-x_predecim, ps); in calc_dma_rotation_offset()
2021 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + in calc_dma_rotation_offset()
2028 *offset1 = screen_width * (fbh - 1) * ps; in calc_dma_rotation_offset()
2030 *offset0 = *offset1 - field_offset * screen_width * ps; in calc_dma_rotation_offset()
2033 *row_inc = pixinc(1 - y_predecim * screen_width * 2 - in calc_dma_rotation_offset()
2044 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; in calc_dma_rotation_offset()
2046 *offset0 = *offset1 - field_offset * ps; in calc_dma_rotation_offset()
2049 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - in calc_dma_rotation_offset()
2050 y_predecim - (fieldmode ? 1 : 0), in calc_dma_rotation_offset()
2052 *pix_inc = pixinc(-x_predecim * screen_width, ps); in calc_dma_rotation_offset()
2061 static void calc_tiler_rotation_offset(u16 screen_width, u16 width, in calc_tiler_rotation_offset() argument
2080 DSSDBG("scrw %d, width %d\n", screen_width, width); in calc_tiler_rotation_offset()
2091 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + in calc_tiler_rotation_offset()
2106 u16 width, u16 height, u16 out_width, u16 out_height, in check_horiz_timing_omap3() argument
2115 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; in check_horiz_timing_omap3()
2120 if (out_width < width) in check_horiz_timing_omap3()
2122 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); in check_horiz_timing_omap3()
2125 return -EINVAL; in check_horiz_timing_omap3()
2127 /* FIXME add checks for 3-tap filter once the limitations are known */ in check_horiz_timing_omap3()
2133 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2134 * during nonactive - pos_x period. in check_horiz_timing_omap3()
2136 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2137 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", in check_horiz_timing_omap3()
2138 val, max(0, ds - 2) * width); in check_horiz_timing_omap3()
2139 if (val < max(0, ds - 2) * width) in check_horiz_timing_omap3()
2140 return -EINVAL; in check_horiz_timing_omap3()
2145 * DS - 1 lines should be loaded during nonactive period. in check_horiz_timing_omap3()
2148 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", in check_horiz_timing_omap3()
2149 val, max(0, ds - 1) * width); in check_horiz_timing_omap3()
2150 if (val < max(0, ds - 1) * width) in check_horiz_timing_omap3()
2151 return -EINVAL; in check_horiz_timing_omap3()
2157 const struct omap_video_timings *mgr_timings, u16 width, in calc_core_clk_five_taps() argument
2164 if (height <= out_height && width <= out_width) in calc_core_clk_five_taps()
2168 unsigned int ppl = mgr_timings->x_res; in calc_core_clk_five_taps()
2178 tmp = (u64)pclk * (height - 2 * out_height) * out_width; in calc_core_clk_five_taps()
2179 do_div(tmp, 2 * out_height * (ppl - out_width)); in calc_core_clk_five_taps()
2184 if (width > out_width) { in calc_core_clk_five_taps()
2185 tmp = (u64)pclk * width; in calc_core_clk_five_taps()
2196 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, in calc_core_clk_24xx() argument
2199 if (height > out_height && width > out_width) in calc_core_clk_24xx()
2205 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, in calc_core_clk_34xx() argument
2215 if (width > 3 * out_width) in calc_core_clk_34xx()
2217 else if (width > 2 * out_width) in calc_core_clk_34xx()
2219 else if (width > out_width) in calc_core_clk_34xx()
2231 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, in calc_core_clk_44xx() argument
2243 if (width > out_width) in calc_core_clk_44xx()
2244 return DIV_ROUND_UP(pclk, out_width) * width; in calc_core_clk_44xx()
2251 u16 width, u16 height, u16 out_width, u16 out_height, in dispc_ovl_calc_scaling_24xx() argument
2266 in_width = width / *decim_x; in dispc_ovl_calc_scaling_24xx()
2267 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2285 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2289 DSSERR("Cannot scale max input width exceeded"); in dispc_ovl_calc_scaling_24xx()
2290 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2297 u16 width, u16 height, u16 out_width, u16 out_height, in dispc_ovl_calc_scaling_34xx() argument
2309 in_width = width / *decim_x; in dispc_ovl_calc_scaling_34xx()
2322 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2358 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2364 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2369 DSSERR("width exceeds maximum width possible"); in dispc_ovl_calc_scaling_34xx()
2370 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2375 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2382 u16 width, u16 height, u16 out_width, u16 out_height, in dispc_ovl_calc_scaling_44xx() argument
2401 *decim_x = DIV_ROUND_UP(width, in_width_max); in dispc_ovl_calc_scaling_44xx()
2405 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2408 in_width = width / *decim_x; in dispc_ovl_calc_scaling_44xx()
2413 DSSERR("Cannot scale width exceeds max line width"); in dispc_ovl_calc_scaling_44xx()
2414 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2417 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2423 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2428 u16 width, u16 height, u16 out_width, u16 out_height, in dispc_ovl_calc_scaling() argument
2438 if (width == out_width && height == out_height) in dispc_ovl_calc_scaling()
2441 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { in dispc_ovl_calc_scaling()
2443 return -EINVAL; in dispc_ovl_calc_scaling()
2447 return -EINVAL; in dispc_ovl_calc_scaling()
2468 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); in dispc_ovl_calc_scaling()
2471 if (decim_x > *x_predecim || out_width > width * 8) in dispc_ovl_calc_scaling()
2472 return -EINVAL; in dispc_ovl_calc_scaling()
2475 return -EINVAL; in dispc_ovl_calc_scaling()
2477 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, in dispc_ovl_calc_scaling()
2484 …DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req cl… in dispc_ovl_calc_scaling()
2485 width, height, in dispc_ovl_calc_scaling()
2487 out_width / width, DIV_FRAC(out_width, width), in dispc_ovl_calc_scaling()
2491 width / decim_x, height / decim_y, in dispc_ovl_calc_scaling()
2492 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), in dispc_ovl_calc_scaling()
2503 return -EINVAL; in dispc_ovl_calc_scaling()
2519 u16 in_height = oi->height; in dispc_ovl_check()
2520 u16 in_width = oi->width; in dispc_ovl_check()
2521 bool ilace = timings->interlace; in dispc_ovl_check()
2523 int pos_x = oi->pos_x; in dispc_ovl_check()
2527 out_width = oi->out_width == 0 ? oi->width : oi->out_width; in dispc_ovl_check()
2528 out_height = oi->out_height == 0 ? oi->height : oi->out_height; in dispc_ovl_check()
2530 if (ilace && oi->height == out_height) in dispc_ovl_check()
2542 if (!dss_feat_color_mode_supported(plane, oi->color_mode)) in dispc_ovl_check()
2543 return -EINVAL; in dispc_ovl_check()
2546 in_height, out_width, out_height, oi->color_mode, in dispc_ovl_check()
2548 oi->rotation_type, false); in dispc_ovl_check()
2554 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, in dispc_ovl_setup_common() argument
2570 u16 in_width = width; in dispc_ovl_setup_common()
2572 bool ilace = mgr_timings->interlace; in dispc_ovl_setup_common()
2577 return -EINVAL; in dispc_ovl_setup_common()
2584 DSSERR("input width %d is not even for YUV format\n", in dispc_ovl_setup_common()
2586 return -EINVAL; in dispc_ovl_setup_common()
2594 out_width = out_width == 0 ? width : out_width; in dispc_ovl_setup_common()
2612 return -EINVAL; in dispc_ovl_setup_common()
2633 DSSDBG("predecimated input width is not even for YUV format\n"); in dispc_ovl_setup_common()
2634 DSSDBG("adjusting input width %d -> %d\n", in dispc_ovl_setup_common()
2714 if (dispc.feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2715 row_inc += pix_inc - 1; in dispc_ovl_setup_common()
2720 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, in dispc_ovl_setup_common()
2757 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" in dispc_ovl_setup()
2759 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, in dispc_ovl_setup()
2760 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, in dispc_ovl_setup()
2761 oi->color_mode, oi->rotation, oi->mirror, channel, replication); in dispc_ovl_setup()
2763 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2764 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, in dispc_ovl_setup()
2765 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, in dispc_ovl_setup()
2766 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, in dispc_ovl_setup()
2767 oi->rotation_type, replication, mgr_timings, mem_to_mem); in dispc_ovl_setup()
2878 dispc_mgr_set_default_color(channel, info->default_color); in dispc_mgr_setup()
2879 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); in dispc_mgr_setup()
2880 dispc_mgr_enable_trans_key(channel, info->trans_enabled); in dispc_mgr_setup()
2882 info->partial_alpha_enabled); in dispc_mgr_setup()
2884 dispc_mgr_enable_cpr(channel, info->cpr_enable); in dispc_mgr_setup()
2885 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); in dispc_mgr_setup()
2952 dispc_mgr_set_io_pad_mode(config->io_pad_mode); in dispc_mgr_set_lcd_config()
2954 dispc_mgr_enable_stallmode(channel, config->stallmode); in dispc_mgr_set_lcd_config()
2955 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
2957 dispc_mgr_set_clock_div(channel, &config->clock_info); in dispc_mgr_set_lcd_config()
2959 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); in dispc_mgr_set_lcd_config()
2961 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
2967 static bool _dispc_mgr_size_ok(u16 width, u16 height) in _dispc_mgr_size_ok() argument
2969 return width <= dispc.feat->mgr_width_max && in _dispc_mgr_size_ok()
2970 height <= dispc.feat->mgr_height_max; in _dispc_mgr_size_ok()
2976 if (hsw < 1 || hsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2977 hfp < 1 || hfp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2978 hbp < 1 || hbp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2979 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2980 vfp < 0 || vfp > dispc.feat->vp_max || in _dispc_lcd_timings_ok()
2981 vbp < 0 || vbp > dispc.feat->vp_max) in _dispc_lcd_timings_ok()
2990 return pclk <= dispc.feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
2992 return pclk <= dispc.feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
2998 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) in dispc_mgr_timings_ok()
3001 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) in dispc_mgr_timings_ok()
3006 if (timings->interlace) in dispc_mgr_timings_ok()
3009 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, in dispc_mgr_timings_ok()
3010 timings->hbp, timings->vsw, timings->vfp, in dispc_mgr_timings_ok()
3011 timings->vbp)) in dispc_mgr_timings_ok()
3030 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3031 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3032 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3033 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3034 FLD_VAL(vfp, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3035 FLD_VAL(vbp, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3106 if (dispc.feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3154 ht = timings->pixelclock / xtot; in dispc_mgr_set_timings()
3155 vt = timings->pixelclock / xtot / ytot; in dispc_mgr_set_timings()
3157 DSSDBG("pck %u\n", timings->pixelclock); in dispc_mgr_set_timings()
3211 r = pll->cinfo.clkout[0]; in dispc_fclk_rate()
3218 r = pll->cinfo.clkout[0]; in dispc_fclk_rate()
3249 r = pll->cinfo.clkout[0]; in dispc_mgr_lclk_rate()
3256 r = pll->cinfo.clkout[0]; in dispc_mgr_lclk_rate()
3328 seq_printf(s, "- %s -\n", mgr_desc[channel].name); in dispc_dump_clocks_channel()
3338 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks_channel()
3340 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", in dispc_dump_clocks_channel()
3353 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3359 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); in dispc_dump_clocks()
3362 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3366 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks()
3398 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) in dispc_dump_regs()
3432 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ in dispc_dump_regs()
3501 if (dispc.feat->has_writeback) { in dispc_dump_regs()
3536 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ in dispc_dump_regs()
3579 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) in dispc_calc_clock_rates()
3580 return -EINVAL; in dispc_calc_clock_rates()
3581 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) in dispc_calc_clock_rates()
3582 return -EINVAL; in dispc_calc_clock_rates()
3584 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; in dispc_calc_clock_rates()
3585 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_calc_clock_rates()
3653 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); in dispc_mgr_set_clock_div()
3654 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); in dispc_mgr_set_clock_div()
3656 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); in dispc_mgr_set_clock_div()
3666 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3667 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3669 cinfo->lck = fck / cinfo->lck_div; in dispc_mgr_get_clock_div()
3670 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_mgr_get_clock_div()
3743 if (dispc.feat->mstandby_workaround) in _omap_dispc_initial_config()
3899 return -EBUSY; in dispc_request_irq()
3907 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, in dispc_request_irq()
3920 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); in dispc_free_irq()
3934 struct device_node *np = pdev->dev.of_node; in dispc_bind()
3942 return -ENODEV; in dispc_bind()
3947 return -EINVAL; in dispc_bind()
3950 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, in dispc_bind()
3954 return -ENOMEM; in dispc_bind()
3960 return -ENODEV; in dispc_bind()
3963 if (np && of_property_read_bool(np, "syscon-pol")) { in dispc_bind()
3964 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
3966 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); in dispc_bind()
3970 if (of_property_read_u32_index(np, "syscon-pol", 1, in dispc_bind()
3972 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); in dispc_bind()
3973 return -EINVAL; in dispc_bind()
3977 pm_runtime_enable(&pdev->dev); in dispc_bind()
3986 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
3998 pm_runtime_disable(&pdev->dev); in dispc_bind()
4017 return component_add(&pdev->dev, &dispc_component_ops); in dispc_probe()
4022 component_del(&pdev->dev, &dispc_component_ops); in dispc_remove()
4065 { .compatible = "ti,omap2-dispc", },
4066 { .compatible = "ti,omap3-dispc", },
4067 { .compatible = "ti,omap4-dispc", },
4068 { .compatible = "ti,omap5-dispc", },
4069 { .compatible = "ti,dra7-dispc", },