include/asm/MC68EZ328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8  * Based on include/asm-m68knommu/MC68332.h
27  * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
40 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
43 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
53  * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN		0x0001		/* Chip-Select Enable */
85 #define CSA_SIZ_MASK	0x000e		/* Chip-Select Size */
89 #define CSA_BSW		0x0080		/* Data Bus Width */
91 #define CSA_RO		0x8000		/* Read-Only */
93 #define CSB_EN		0x0001		/* Chip-Select Enable */
94 #define CSB_SIZ_MASK	0x000e		/* Chip-Select Size */
98 #define CSB_BSW		0x0080		/* Data Bus Width */
104 #define CSB_RO		0x8000		/* Read-Only */
106 #define CSC_EN		0x0001		/* Chip-Select Enable */
107 #define CSC_SIZ_MASK	0x000e		/* Chip-Select Size */
111 #define CSC_BSW		0x0080		/* Data Bus Width */
117 #define CSC_RO		0x8000		/* Read-Only */
119 #define CSD_EN		0x0001		/* Chip-Select Enable */
120 #define CSD_SIZ_MASK	0x000e		/* Chip-Select Size */
124 #define CSD_BSW		0x0080		/* Data Bus Width */
132 #define CSD_RO		0x8000		/* Read-Only */
135  * Emulation Chip-Select Register
145  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
163 /* '328-compatible definitions */
186 #define PCTRL_WIDTH_MASK	0x1f	/* CPU Clock bursts width */
192  * 0xFFFFF3xx -- Interrupt Controller
236 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
249 /* '328-compatible definitions */
262 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
275 /* '328-compatible definitions */
291 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
304 /* '328-compatible definitions */
320 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
333 /* '328-compatible definitions */
339  * 0xFFFFF4xx -- Parallel Ports
348 #define PAPUEN_ADDR	0xfffff402		/* Port A Pull-Up enable reg */
361 #define PBPUEN_ADDR	0xfffff40a		/* Port B Pull-Up enable reg */
385 #define PCPDEN_ADDR	0xfffff412		/* Port C Pull-Down enb. reg */
409 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
441 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
465 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
489 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
508  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
523 #define PMNC_FIFOAV		0x0020	/* FIFO Available */
525 #define PWMC_IRQ		0x0080	/* Interrupt Request (FIFO empty) */
530 /* '328-compatible definitions */
553  * 0xFFFFF6xx -- General-Purpose Timer
575 #define TCTL_FRR		0x0010	/* Free-Run Mode */
577 /* '328-compatible definitions */
587 /* '328-compatible definitions */
597 /* '328-compatible definitions */
607 /* '328-compatible definitions */
617 /* '328-compatible definitions */
630 /* '328-compatible definitions */
636  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
663 /* '328-compatible definitions */
669  * 0xFFFFF9xx -- UART
683 #define USTCNT_RXHE	0x0010	/* Receiver Half-Full Interrupt Enable */
687 #define USTCNT_8_7	0x0100	/* Eight or seven-bit transmission */
696 /* '328-compatible definitions */
715 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
737 #define URX_OLD_DATA	 0x1000	/* Old data in FIFO */
738 #define URX_DATA_READY	 0x2000	/* Data Ready (FIFO not empty) */
739 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
740 #define URX_FIFO_FULL	 0x8000	/* FIFO is Full */
755 #define	UTX_BUSY	 0x0400	/* FIFO is busy, sending a character */
758 #define UTX_TX_AVAIL	 0x2000	/* Transmit FIFO has a slot available */
759 #define UTX_FIFO_HALF	 0x4000	/* Transmit FIFO is half empty */
760 #define UTX_FIFO_EMPTY	 0x8000	/* Transmit FIFO is empty */
762 /* '328-compatible definitions */
775 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
786  * UART Non-integer Prescaler Register
795 #define NIPR_PRE_SEL		0x8000	/* Non-integer prescaler select */
825  * 0xFFFFFAxx -- LCD Controller
835 #define LSSA_SSA_MASK	0x1ffffffe	/* Bits 0 and 29-31 are reserved */
838  * LCD Virtual Page Width Register
844  * LCD Screen Width Register (not compatible with '328 !!!)
849 #define LXMAX_XM_MASK	0x02f0		/* Bits 0-3 and 10-15 are reserved */
857 #define LYMAX_YM_MASK	0x01ff		/* Bits 9-15 are reserved */
881  * LCD Cursor Width and Heigth Register
888 #define LCWCH_CW_MASK	0x1f00		/* Cursor Width */
907 #define LPICF_GS_MASK	 0x03	 /* Gray-Scale Mode */
911 #define LPICF_PBSIZ_MASK 0x0c	/* Panel Bus Width */
952 #define LCKCON_DWS_MASK	 0x0f	/* Display Wait-State */
954 #define LCKCON_DWIDTH	 0x40	/* Display Memory Width  */
957 /* '328-compatible definitions */
1004 #define PWMR_PW_MASK	0x00ff	/* Pulse Width */
1014  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1065 /* '328-compatible definitions */
1076 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1078 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1080 #define RTCISR_HR	0x0020	/* 1-hour interrupt has occurred */
1097 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1099 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */
1101 #define RTCIENR_HR	0x0020	/* 1-hour interrupt enable */
1140  * 0xFFFFFCxx -- DRAM Controller
1176 #define DRAMC_LPR	   0x0004	/* Low-Power Refresh Enable */
1180 #define DRAMC_WS_MASK	   0x00c0	/* Wait-states */
1198  * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1251 #define ICEMSR_BRKIRQ	0x0002	/* A-Line Vector Fetch Detected */