Lines Matching +full:fifo +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
78 /* An unknown HW bug causing the normal FIFO thresholds not to work */
105 u16 width, u16 height, u16 out_width, u16 out_height,
110 u16 width, u16 height, u16 out_width, u16 out_height,
176 /* maps which plane is using a fifo. fifo-id -> plane-id */
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
384 return dispc->feat->num_ovls; in dispc_get_num_ovls()
389 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
396 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
398 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
399 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
407 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
408 if (dispc->feat->features[i] == id) in dispc_has_feature()
416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
522 dispc->ctx_valid = true; in dispc_save_context()
533 if (!dispc->ctx_valid) in dispc_restore_context()
655 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
657 pm_runtime_put_noidle(&dispc->pdev->dev); in dispc_runtime_get()
669 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
670 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
682 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
813 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
864 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
865 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
870 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
875 /* YUV -> RGB, ITU-R BT.601, full range */
878 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
883 /* YUV -> RGB, ITU-R BT.601, limited range */
886 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
891 /* YUV -> RGB, ITU-R BT.709, full range */
894 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
899 /* YUV -> RGB, ITU-R BT.709, limited range */
902 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
972 enum omap_plane_id plane, int width, in dispc_ovl_set_input_size() argument
975 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size()
984 enum omap_plane_id plane, int width, in dispc_ovl_set_output_size() argument
991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_output_size()
1268 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1276 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1285 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1298 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1319 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | in dispc_mgr_set_cpr_coef()
1320 FLD_VAL(coefs->rb, 9, 0); in dispc_mgr_set_cpr_coef()
1321 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | in dispc_mgr_set_cpr_coef()
1322 FLD_VAL(coefs->gb, 9, 0); in dispc_mgr_set_cpr_coef()
1323 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | in dispc_mgr_set_cpr_coef()
1324 FLD_VAL(coefs->bb, 9, 0); in dispc_mgr_set_cpr_coef()
1359 enum omap_channel channel, u16 width, u16 height) in dispc_mgr_set_size() argument
1363 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1364 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1372 int fifo; in dispc_init_fifos() local
1377 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1381 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1382 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1385 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1388 * By default fifos are mapped directly to overlays, fifo 0 to in dispc_init_fifos()
1389 * ovl 0, fifo 1 to ovl 1, etc. in dispc_init_fifos()
1391 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1395 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo in dispc_init_fifos()
1398 * giving GFX plane a larger fifo. WB but should work fine with a in dispc_init_fifos()
1399 * smaller fifo. in dispc_init_fifos()
1401 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1413 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1414 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1418 * Setup default fifo thresholds. in dispc_init_fifos()
1431 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1447 int fifo; in dispc_ovl_get_fifo_size() local
1450 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1451 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1452 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1465 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1478 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", in dispc_ovl_set_fifo_threshold()
1496 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1508 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); in dispc_enable_fifomerge()
1519 * buffer_units, and the fifo thresholds must be buffer_unit aligned. in dispc_ovl_compute_fifo_thresholds()
1521 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1537 * We use the same low threshold for both fifomerge and non-fifomerge in dispc_ovl_compute_fifo_thresholds()
1539 * combined fifo size in dispc_ovl_compute_fifo_thresholds()
1543 *fifo_low = ovl_fifo_size - burst_size * 2; in dispc_ovl_compute_fifo_thresholds()
1544 *fifo_high = total_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1549 * in the FIFO to form a burst in dispc_ovl_compute_fifo_thresholds()
1554 *fifo_low = ovl_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1555 *fifo_high = total_fifo_size - buf_unit; in dispc_ovl_compute_fifo_thresholds()
1592 * As a work-around, set force MFLAG to always on. in dispc_init_mflag()
1600 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1617 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1619 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1756 { 0, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1757 { 1, 2, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1758 { -1, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1759 { -1, 2, -1, 2 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1763 { 0, 1, 0, 1 , -3, 4, -1, 4 }, in dispc_ovl_set_accu_uv()
1764 { -1, 4, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1765 { -1, 1, 0, 1 , -1, 4, -3, 4 }, in dispc_ovl_set_accu_uv()
1766 { -3, 4, -3, 4 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1772 { -1, 1, 0, 1, 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1773 { 0, 1, 0, 1, -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1776 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_accu_uv()
1814 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; in dispc_ovl_set_accu_uv()
1815 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; in dispc_ovl_set_accu_uv()
1816 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; in dispc_ovl_set_accu_uv()
1817 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; in dispc_ovl_set_accu_uv()
1870 accu0 -= accu1; in dispc_ovl_set_scaling_common()
1896 if (!info->is_yuv) { in dispc_ovl_set_scaling_uv()
1988 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_rotation_attrs()
2087 return 1 + (pixels - 1) * ps; in pixinc()
2089 return 1 - (-pixels + 1) * ps; in pixinc()
2094 static void calc_offset(u16 screen_width, u16 width, in calc_offset() argument
2104 DSSDBG("scrw %d, width %d\n", screen_width, width); in calc_offset()
2112 * YUV422 pixel size gives the correct TILER container width. in calc_offset()
2113 * However, 'width' is in pixels and multiplying it with YUV422 in calc_offset()
2117 width *= 2; in calc_offset()
2127 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + in calc_offset()
2141 u16 width, u16 height, u16 out_width, u16 out_height, in check_horiz_timing_omap3() argument
2150 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + in check_horiz_timing_omap3()
2151 vm->hback_porch - out_width; in check_horiz_timing_omap3()
2156 if (out_width < width) in check_horiz_timing_omap3()
2158 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * in check_horiz_timing_omap3()
2162 return -EINVAL; in check_horiz_timing_omap3()
2164 /* FIXME add checks for 3-tap filter once the limitations are known */ in check_horiz_timing_omap3()
2170 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2171 * during nonactive - pos_x period. in check_horiz_timing_omap3()
2173 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2174 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", in check_horiz_timing_omap3()
2175 val, max(0, ds - 2) * width); in check_horiz_timing_omap3()
2176 if (val < max(0, ds - 2) * width) in check_horiz_timing_omap3()
2177 return -EINVAL; in check_horiz_timing_omap3()
2182 * DS - 1 lines should be loaded during nonactive period. in check_horiz_timing_omap3()
2185 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", in check_horiz_timing_omap3()
2186 val, max(0, ds - 1) * width); in check_horiz_timing_omap3()
2187 if (val < max(0, ds - 1) * width) in check_horiz_timing_omap3()
2188 return -EINVAL; in check_horiz_timing_omap3()
2194 const struct videomode *vm, u16 width, in calc_core_clk_five_taps() argument
2201 if (height <= out_height && width <= out_width) in calc_core_clk_five_taps()
2205 unsigned int ppl = vm->hactive; in calc_core_clk_five_taps()
2215 tmp = (u64)pclk * (height - 2 * out_height) * out_width; in calc_core_clk_five_taps()
2216 do_div(tmp, 2 * out_height * (ppl - out_width)); in calc_core_clk_five_taps()
2221 if (width > out_width) { in calc_core_clk_five_taps()
2222 tmp = (u64)pclk * width; in calc_core_clk_five_taps()
2233 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, in calc_core_clk_24xx() argument
2236 if (height > out_height && width > out_width) in calc_core_clk_24xx()
2242 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, in calc_core_clk_34xx() argument
2252 if (width > 3 * out_width) in calc_core_clk_34xx()
2254 else if (width > 2 * out_width) in calc_core_clk_34xx()
2256 else if (width > out_width) in calc_core_clk_34xx()
2268 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, in calc_core_clk_44xx() argument
2280 if (width > out_width) in calc_core_clk_44xx()
2281 return DIV_ROUND_UP(pclk, out_width) * width; in calc_core_clk_44xx()
2289 u16 width, u16 height, in dispc_ovl_calc_scaling_24xx() argument
2300 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2306 in_width = width / *decim_x; in dispc_ovl_calc_scaling_24xx()
2307 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2325 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2329 DSSERR("Cannot scale max input width exceeded\n"); in dispc_ovl_calc_scaling_24xx()
2330 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2338 u16 width, u16 height, in dispc_ovl_calc_scaling_34xx() argument
2348 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2352 in_width = width / *decim_x; in dispc_ovl_calc_scaling_34xx()
2365 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2401 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2407 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2412 DSSERR("width exceeds maximum width possible\n"); in dispc_ovl_calc_scaling_34xx()
2413 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2418 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2426 u16 width, u16 height, in dispc_ovl_calc_scaling_44xx() argument
2437 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2438 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2447 *decim_x = DIV_ROUND_UP(width, in_width_max); in dispc_ovl_calc_scaling_44xx()
2451 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2454 in_width = width / *decim_x; in dispc_ovl_calc_scaling_44xx()
2459 DSSERR("Cannot scale width exceeds max line width\n"); in dispc_ovl_calc_scaling_44xx()
2460 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2475 * be true also for 16-bit color formats. in dispc_ovl_calc_scaling_44xx()
2477 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x); in dispc_ovl_calc_scaling_44xx()
2479 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2482 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2489 return dispc->feat->overlay_caps[plane]; in dispc_ovl_get_caps()
2493 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2500 u16 width, u16 height, in dispc_ovl_calc_scaling() argument
2507 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2508 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2513 if (width == out_width && height == out_height) in dispc_ovl_calc_scaling()
2516 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2517 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2526 return -EINVAL; in dispc_ovl_calc_scaling()
2543 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { in dispc_ovl_calc_scaling()
2545 return -EINVAL; in dispc_ovl_calc_scaling()
2549 return -EINVAL; in dispc_ovl_calc_scaling()
2560 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale); in dispc_ovl_calc_scaling()
2563 if (decim_x > *x_predecim || out_width > width * 8) in dispc_ovl_calc_scaling()
2564 return -EINVAL; in dispc_ovl_calc_scaling()
2567 return -EINVAL; in dispc_ovl_calc_scaling()
2569 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2577 …DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req cl… in dispc_ovl_calc_scaling()
2578 width, height, in dispc_ovl_calc_scaling()
2580 out_width / width, DIV_FRAC(out_width, width), in dispc_ovl_calc_scaling()
2584 width / decim_x, height / decim_y, in dispc_ovl_calc_scaling()
2585 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), in dispc_ovl_calc_scaling()
2596 return -EINVAL; in dispc_ovl_calc_scaling()
2604 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height) in dispc_ovl_get_max_size() argument
2606 *width = dispc->feat->ovl_width_max; in dispc_ovl_get_max_size()
2607 *height = dispc->feat->ovl_height_max; in dispc_ovl_get_max_size()
2615 u16 width, u16 height, in dispc_ovl_setup_common() argument
2634 u16 in_width = width; in dispc_ovl_setup_common()
2636 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); in dispc_ovl_setup_common()
2645 pclk = vm->pixelclock; in dispc_ovl_setup_common()
2648 return -EINVAL; in dispc_ovl_setup_common()
2650 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2651 DSSERR("input width %d is not even for YUV format\n", in_width); in dispc_ovl_setup_common()
2652 return -EINVAL; in dispc_ovl_setup_common()
2655 out_width = out_width == 0 ? width : out_width; in dispc_ovl_setup_common()
2674 return -EINVAL; in dispc_ovl_setup_common()
2690 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2691 DSSDBG("predecimated input width is not even for YUV format\n"); in dispc_ovl_setup_common()
2692 DSSDBG("adjusting input width %d -> %d\n", in dispc_ovl_setup_common()
2698 if (info->is_yuv) in dispc_ovl_setup_common()
2742 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2753 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2754 row_inc += pix_inc - 1; in dispc_ovl_setup_common()
2759 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, in dispc_ovl_setup_common()
2796 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2799 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" in dispc_ovl_setup()
2801 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, in dispc_ovl_setup()
2802 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, in dispc_ovl_setup()
2803 oi->fourcc, oi->rotation, channel, replication); in dispc_ovl_setup()
2807 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2808 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, in dispc_ovl_setup()
2809 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, in dispc_ovl_setup()
2810 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, in dispc_ovl_setup()
2811 oi->rotation_type, replication, vm, mem_to_mem, in dispc_ovl_setup()
2812 oi->color_encoding, oi->color_range); in dispc_ovl_setup()
2829 int in_width = vm->hactive; in dispc_wb_setup()
2830 int in_height = vm->vactive; in dispc_wb_setup()
2834 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_wb_setup()
2837 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " in dispc_wb_setup()
2838 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, in dispc_wb_setup()
2839 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); in dispc_wb_setup()
2841 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2842 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, in dispc_wb_setup()
2843 wi->height, wi->fourcc, wi->rotation, zorder, in dispc_wb_setup()
2844 wi->pre_mult_alpha, global_alpha, wi->rotation_type, in dispc_wb_setup()
2850 switch (wi->fourcc) { in dispc_wb_setup()
2884 wbdelay = vm->vsync_len + vm->vback_porch; in dispc_wb_setup()
2886 wbdelay = vm->vfront_porch + vm->vsync_len + in dispc_wb_setup()
2887 vm->vback_porch; in dispc_wb_setup()
2889 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_wb_setup()
2903 return dispc->feat->has_writeback; in dispc_has_writeback()
3001 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
3002 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
3003 info->trans_key); in dispc_mgr_setup()
3004 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
3006 info->partial_alpha_enabled); in dispc_mgr_setup()
3008 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
3009 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
3080 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3082 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3083 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3085 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3087 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3089 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3095 u16 width, u16 height) in _dispc_mgr_size_ok() argument
3097 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3098 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3105 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3106 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3107 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3108 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3109 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3110 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3120 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3122 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3129 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3132 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3137 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_mgr_check_timings()
3140 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3141 vm->hfront_porch, vm->hback_porch, in dispc_mgr_check_timings()
3142 vm->vsync_len, vm->vfront_porch, in dispc_mgr_check_timings()
3143 vm->vback_porch)) in dispc_mgr_check_timings()
3157 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3158 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3159 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3160 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3161 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3162 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3167 vs = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3168 hs = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3169 de = !!(vm->flags & DISPLAY_FLAGS_DE_LOW); in _dispc_mgr_set_lcd_timings()
3170 ipc = !!(vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE); in _dispc_mgr_set_lcd_timings()
3172 rf = !!(vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE); in _dispc_mgr_set_lcd_timings()
3182 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3187 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3202 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3213 return -1; in vm_flag_to_int()
3239 ht = vm->pixelclock / xtot; in dispc_mgr_set_timings()
3240 vt = vm->pixelclock / xtot / ytot; in dispc_mgr_set_timings()
3242 DSSDBG("pck %lu\n", vm->pixelclock); in dispc_mgr_set_timings()
3258 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3279 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3297 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3300 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3305 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3308 r = pll->cinfo.clkout[clkout_idx]; in dispc_fclk_rate()
3325 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3328 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3333 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3336 r = pll->cinfo.clkout[clkout_idx]; in dispc_mgr_lclk_rate()
3361 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3367 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3372 return dispc->core_clk_rate; in dispc_core_clk_rate()
3408 seq_printf(s, "- %s -\n", mgr_desc[channel].name); in dispc_dump_clocks_channel()
3410 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3417 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks_channel()
3419 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", in dispc_dump_clocks_channel()
3432 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3434 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3438 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3441 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3445 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks()
3461 struct dispc_device *dispc = s->private; in dispc_dump_regs()
3479 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3513 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ in dispc_dump_regs()
3582 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3617 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ in dispc_dump_regs()
3663 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) in dispc_calc_clock_rates()
3664 return -EINVAL; in dispc_calc_clock_rates()
3665 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) in dispc_calc_clock_rates()
3666 return -EINVAL; in dispc_calc_clock_rates()
3668 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; in dispc_calc_clock_rates()
3669 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_calc_clock_rates()
3692 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3695 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3738 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); in dispc_mgr_set_clock_div()
3739 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); in dispc_mgr_set_clock_div()
3741 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3742 cinfo->pck_div); in dispc_mgr_set_clock_div()
3753 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3754 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3756 cinfo->lck = fck / cinfo->lck_div; in dispc_mgr_get_clock_div()
3757 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_mgr_get_clock_div()
3801 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3804 return gdesc->len; in dispc_mgr_gamma_size()
3811 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3816 for (i = 0; i < gdesc->len; ++i) { in dispc_mgr_write_gamma_table()
3819 if (gdesc->has_index) in dispc_mgr_write_gamma_table()
3824 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3832 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3857 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3861 channel, length, gdesc->len); in dispc_mgr_set_gamma()
3863 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3871 for (i = 0; i < length - 1; ++i) { in dispc_mgr_set_gamma()
3872 uint first = i * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3873 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3874 uint w = last - first; in dispc_mgr_set_gamma()
3882 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; in dispc_mgr_set_gamma()
3883 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; in dispc_mgr_set_gamma()
3884 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; in dispc_mgr_set_gamma()
3886 r >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3887 g >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3888 b >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3890 table[first + j] = (r << (gdesc->bits * 2)) | in dispc_mgr_set_gamma()
3891 (g << gdesc->bits) | b; in dispc_mgr_set_gamma()
3895 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3903 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3906 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3918 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3921 return -ENOMEM; in dispc_init_gamma_tables()
3923 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3942 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3946 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3950 * func-clock auto-gating. For newer versions in _omap_dispc_initial_config()
3951 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. in _omap_dispc_initial_config()
3954 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3965 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
4256 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4257 * cannot scale an image width larger than 768.
4515 if (!dispc->is_enabled) in dispc_irq_handler()
4518 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4526 if (dispc->user_handler != NULL) in dispc_request_irq()
4527 return -EBUSY; in dispc_request_irq()
4529 dispc->user_handler = handler; in dispc_request_irq()
4530 dispc->user_data = dev_id; in dispc_request_irq()
4535 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4538 dispc->user_handler = NULL; in dispc_request_irq()
4539 dispc->user_data = NULL; in dispc_request_irq()
4547 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4549 dispc->user_handler = NULL; in dispc_free_irq()
4550 dispc->user_data = NULL; in dispc_free_irq()
4558 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4566 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4600 .width = 1, .height = 1,
4637 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4640 i734_buf.size = i734.ovli.width * i734.ovli.height * in dispc_errata_i734_wa_init()
4643 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4646 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4648 return -ENOMEM; in dispc_errata_i734_wa_init()
4656 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4659 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4672 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4691 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4709 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4725 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4726 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4727 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4728 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4729 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4750 struct device_node *np = pdev->dev.of_node; in dispc_bind()
4754 return -ENOMEM; in dispc_bind()
4756 dispc->pdev = pdev; in dispc_bind()
4758 dispc->dss = dss; in dispc_bind()
4761 * The OMAP3-based models can't be told apart using the compatible in dispc_bind()
4766 dispc->feat = soc->data; in dispc_bind()
4768 dispc->feat = device_get_match_data(&pdev->dev); in dispc_bind()
4774 dispc->base = devm_platform_ioremap_resource(pdev, 0); in dispc_bind()
4775 if (IS_ERR(dispc->base)) { in dispc_bind()
4776 r = PTR_ERR(dispc->base); in dispc_bind()
4780 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4781 if (dispc->irq < 0) { in dispc_bind()
4783 r = -ENODEV; in dispc_bind()
4787 if (np && of_property_read_bool(np, "syscon-pol")) { in dispc_bind()
4788 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4789 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4790 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); in dispc_bind()
4791 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4795 if (of_property_read_u32_index(np, "syscon-pol", 1, in dispc_bind()
4796 &dispc->syscon_pol_offset)) { in dispc_bind()
4797 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); in dispc_bind()
4798 r = -EINVAL; in dispc_bind()
4807 pm_runtime_enable(&pdev->dev); in dispc_bind()
4816 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
4821 dss->dispc = dispc; in dispc_bind()
4823 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4829 pm_runtime_disable(&pdev->dev); in dispc_bind()
4838 struct dss_device *dss = dispc->dss; in dispc_unbind()
4840 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4842 dss->dispc = NULL; in dispc_unbind()
4858 return component_add(&pdev->dev, &dispc_component_ops); in dispc_probe()
4863 component_del(&pdev->dev, &dispc_component_ops); in dispc_remove()
4870 dispc->is_enabled = false; in dispc_runtime_suspend()
4874 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4901 dispc->is_enabled = true; in dispc_runtime_resume()