Lines Matching +full:fifo +full:- +full:width
3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); in nv3LockUnlock()
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); in nv3LockUnlock()
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in nv4LockUnlock()
126 cursor = chip->CurrentState->cursor1; in ShowHideCursor()
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | in ShowHideCursor()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); in ShowHideCursor()
259 cur = ainfo->cur; in nv3_iterate()
263 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; in nv3_iterate()
268 if (ainfo->vid_en) in nv3_iterate()
270 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; in nv3_iterate()
271 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; in nv3_iterate()
272 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
273 vfsize = ns * ainfo->vdrain_rate / 1000000; in nv3_iterate()
274 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; in nv3_iterate()
276 if (state->enable_mp) in nv3_iterate()
278 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; in nv3_iterate()
280 if (ainfo->gr_en) in nv3_iterate()
282 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; in nv3_iterate()
283 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; in nv3_iterate()
284 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; in nv3_iterate()
285 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; in nv3_iterate()
286 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; in nv3_iterate()
289 if (!state->gr_during_vid && ainfo->vid_en) in nv3_iterate()
290 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) in nv3_iterate()
292 else if (ainfo->mocc < 0) in nv3_iterate()
294 else if (ainfo->gocc< ainfo->by_gfacc) in nv3_iterate()
297 else switch (ainfo->priority) in nv3_iterate()
300 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
302 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
304 else if (ainfo->mocc<0) in nv3_iterate()
309 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
311 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
313 else if (ainfo->mocc<0) in nv3_iterate()
318 if (ainfo->mocc<0) in nv3_iterate()
320 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
322 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
334 else if (ainfo->first_vacc) misses = vmisses; in nv3_iterate()
336 ainfo->first_vacc = 0; in nv3_iterate()
339 … ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; in nv3_iterate()
340 vlwm = ns * ainfo->vdrain_rate/ 1000000; in nv3_iterate()
341 vlwm = ainfo->vocc - vlwm; in nv3_iterate()
343 …ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mcl… in nv3_iterate()
344 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; in nv3_iterate()
345 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; in nv3_iterate()
346 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; in nv3_iterate()
350 else if (ainfo->first_gacc) misses = gmisses; in nv3_iterate()
352 ainfo->first_gacc = 0; in nv3_iterate()
355 … ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; in nv3_iterate()
356 glwm = ns * ainfo->gdrain_rate/1000000; in nv3_iterate()
357 glwm = ainfo->gocc - glwm; in nv3_iterate()
359 …ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mcl… in nv3_iterate()
360 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; in nv3_iterate()
361 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; in nv3_iterate()
362 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; in nv3_iterate()
366 else if (ainfo->first_macc) misses = mmisses; in nv3_iterate()
368 ainfo->first_macc = 0; in nv3_iterate()
369 … ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; in nv3_iterate()
370 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; in nv3_iterate()
371 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; in nv3_iterate()
372 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; in nv3_iterate()
377 ainfo->converged = 0; in nv3_iterate()
380 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
381 tmp = ns * ainfo->gdrain_rate/1000000; in nv3_iterate()
382 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) in nv3_iterate()
384 ainfo->converged = 0; in nv3_iterate()
387 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
388 tmp = ns * ainfo->vdrain_rate/1000000; in nv3_iterate()
389 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) in nv3_iterate()
391 ainfo->converged = 0; in nv3_iterate()
394 if (abs(ainfo->gocc) > max_gfsize) in nv3_iterate()
396 ainfo->converged = 0; in nv3_iterate()
399 if (abs(ainfo->vocc) > VFIFO_SIZE) in nv3_iterate()
401 ainfo->converged = 0; in nv3_iterate()
404 if (abs(ainfo->mocc) > MFIFO_SIZE) in nv3_iterate()
406 ainfo->converged = 0; in nv3_iterate()
411 ainfo->converged = 0; in nv3_iterate()
416 ainfo->converged = 0; in nv3_iterate()
421 ainfo->converged = 0; in nv3_iterate()
432 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; in nv3_arb()
434 if (state->mem_aligned) gmisses = 2; in nv3_arb()
437 eburst_size = state->memory_width * 1; in nv3_arb()
439 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; in nv3_arb()
440 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; in nv3_arb()
441 ainfo->wcmocc = 0; in nv3_arb()
442 ainfo->wcgocc = 0; in nv3_arb()
443 ainfo->wcvocc = 0; in nv3_arb()
444 ainfo->wcvlwm = 0; in nv3_arb()
445 ainfo->wcglwm = 0; in nv3_arb()
446 ainfo->engine_en = 1; in nv3_arb()
447 ainfo->converged = 1; in nv3_arb()
448 if (ainfo->engine_en) in nv3_arb()
450 …ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->… in nv3_arb()
451 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; in nv3_arb()
452 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; in nv3_arb()
453 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; in nv3_arb()
454 ainfo->cur = ENGINE; in nv3_arb()
455 ainfo->first_vacc = 1; in nv3_arb()
456 ainfo->first_gacc = 1; in nv3_arb()
457 ainfo->first_macc = 1; in nv3_arb()
460 if (state->enable_mp) in nv3_arb()
462 …mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycl… in nv3_arb()
463 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; in nv3_arb()
464 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; in nv3_arb()
465 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; in nv3_arb()
466 ainfo->cur = MPORT; in nv3_arb()
467 ainfo->first_vacc = 1; in nv3_arb()
468 ainfo->first_gacc = 1; in nv3_arb()
469 ainfo->first_macc = 0; in nv3_arb()
472 if (ainfo->gr_en) in nv3_arb()
474 ainfo->first_vacc = 1; in nv3_arb()
475 ainfo->first_gacc = 0; in nv3_arb()
476 ainfo->first_macc = 1; in nv3_arb()
477 …gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh… in nv3_arb()
478 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; in nv3_arb()
479 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; in nv3_arb()
480 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; in nv3_arb()
481 ainfo->cur = GRAPHICS; in nv3_arb()
484 if (ainfo->vid_en) in nv3_arb()
486 ainfo->first_vacc = 0; in nv3_arb()
487 ainfo->first_gacc = 1; in nv3_arb()
488 ainfo->first_macc = 1; in nv3_arb()
489 …vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh… in nv3_arb()
490 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; in nv3_arb()
491 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; in nv3_arb()
492 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; in nv3_arb()
493 ainfo->cur = VIDEO; in nv3_arb()
496 if (ainfo->converged) in nv3_arb()
498 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; in nv3_arb()
499 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; in nv3_arb()
500 res_info->graphics_burst_size = ainfo->gburst_size; in nv3_arb()
501 res_info->video_burst_size = ainfo->vburst_size; in nv3_arb()
502 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); in nv3_arb()
503 res_info->media_hi_priority = (ainfo->priority == MPORT); in nv3_arb()
504 if (res_info->video_lwm > 160) in nv3_arb()
506 res_info->graphics_lwm = 256; in nv3_arb()
507 res_info->video_lwm = 128; in nv3_arb()
508 res_info->graphics_burst_size = 64; in nv3_arb()
509 res_info->video_burst_size = 64; in nv3_arb()
510 res_info->graphics_hi_priority = 0; in nv3_arb()
511 res_info->media_hi_priority = 0; in nv3_arb()
512 ainfo->converged = 0; in nv3_arb()
515 if (res_info->video_lwm > 128) in nv3_arb()
517 res_info->video_lwm = 128; in nv3_arb()
523 res_info->graphics_lwm = 256; in nv3_arb()
524 res_info->video_lwm = 128; in nv3_arb()
525 res_info->graphics_burst_size = 64; in nv3_arb()
526 res_info->video_burst_size = 64; in nv3_arb()
527 res_info->graphics_hi_priority = 0; in nv3_arb()
528 res_info->media_hi_priority = 0; in nv3_arb()
543 ainfo->priority = p; in nv3_get_param()
544 ainfo->gburst_size = g; in nv3_get_param()
545 ainfo->vburst_size = v; in nv3_get_param()
548 if ((res_info->graphics_lwm + g) > 256) in nv3_get_param()
570 ainfo.vid_en = state->enable_video; in nv3CalcArbitration()
573 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); in nv3CalcArbitration()
574 ainfo.vdrain_rate = (int) state->pclk_khz * 2; in nv3CalcArbitration()
575 if (state->video_scale != 0) in nv3CalcArbitration()
576 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; in nv3CalcArbitration()
578 res_info->rtl_values = 0; in nv3CalcArbitration()
579 if (!state->gr_during_vid && state->enable_video) in nv3CalcArbitration()
586 save_info.video_lwm = res_info->video_lwm; in nv3CalcArbitration()
587 save_info.video_burst_size = res_info->video_burst_size; in nv3CalcArbitration()
591 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); in nv3CalcArbitration()
595 res_info->video_lwm = save_info.video_lwm; in nv3CalcArbitration()
596 res_info->video_burst_size = save_info.video_burst_size; in nv3CalcArbitration()
597 res_info->valid = res_gr & res_vid; in nv3CalcArbitration()
604 res_info->valid = ainfo.converged; in nv3CalcArbitration()
620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
622 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv3UpdateArbitrationSettings()
627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
654 nv4_fifo_info *fifo, in nv4CalcArbitration() argument
658 int data, pagemiss, cas,width, video_enable, bpp; in nv4CalcArbitration() local
665 fifo->valid = 1; in nv4CalcArbitration()
666 pclk_freq = arb->pclk_khz; in nv4CalcArbitration()
667 mclk_freq = arb->mclk_khz; in nv4CalcArbitration()
668 nvclk_freq = arb->nvclk_khz; in nv4CalcArbitration()
669 pagemiss = arb->mem_page_miss; in nv4CalcArbitration()
670 cas = arb->mem_latency; in nv4CalcArbitration()
671 width = arb->memory_width >> 6; in nv4CalcArbitration()
672 video_enable = arb->enable_video; in nv4CalcArbitration()
673 bpp = arb->pix_bpp; in nv4CalcArbitration()
674 mp_enable = arb->enable_mp; in nv4CalcArbitration()
703 fifo->valid = 1; in nv4CalcArbitration()
717 if (nvclk_freq * 2 > mclk_freq * width) in nv4CalcArbitration()
720 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; in nv4CalcArbitration()
726 if (vlwm > (256-64)) vbs = 32; in nv4CalcArbitration()
727 if (nvclk_freq * 2 > mclk_freq * width) in nv4CalcArbitration()
730 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; in nv4CalcArbitration()
751 m1 = clwm + cbs - 512; in nv4CalcArbitration()
756 fifo->valid = 0; in nv4CalcArbitration()
759 mclk_extra--; in nv4CalcArbitration()
765 fifo->valid = 0; in nv4CalcArbitration()
768 mclk_extra--; in nv4CalcArbitration()
775 fifo->valid = 0; in nv4CalcArbitration()
778 mclk_extra--; in nv4CalcArbitration()
784 fifo->graphics_lwm = data; in nv4CalcArbitration()
785 fifo->graphics_burst_size = 128; in nv4CalcArbitration()
787 fifo->video_lwm = data; in nv4CalcArbitration()
788 fifo->video_burst_size = vbs; in nv4CalcArbitration()
804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
806 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
807 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
809 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings()
835 nv10_fifo_info *fifo, in nv10CalcArbitration() argument
839 int data, pagemiss, width, video_enable, bpp; in nv10CalcArbitration() local
852 fifo->valid = 1; in nv10CalcArbitration()
853 pclk_freq = arb->pclk_khz; /* freq in KHz */ in nv10CalcArbitration()
854 mclk_freq = arb->mclk_khz; in nv10CalcArbitration()
855 nvclk_freq = arb->nvclk_khz; in nv10CalcArbitration()
856 pagemiss = arb->mem_page_miss; in nv10CalcArbitration()
857 width = arb->memory_width/64; in nv10CalcArbitration()
858 video_enable = arb->enable_video; in nv10CalcArbitration()
859 bpp = arb->pix_bpp; in nv10CalcArbitration()
860 mp_enable = arb->enable_mp; in nv10CalcArbitration()
867 nvclks = 3; /* lwm -> sync. */ in nv10CalcArbitration()
875 mclks += 2; /* tc_req latency fifo */ in nv10CalcArbitration()
880 if (arb->memory_type == 0) in nv10CalcArbitration()
881 if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()
886 if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()
891 if ((!video_enable) && (arb->memory_width == 128)) in nv10CalcArbitration()
916 fifo->valid = 1; in nv10CalcArbitration()
950 clwm++; /* fixed point <= float_point - 1. Fixes that */ in nv10CalcArbitration()
961 clwm++; /* fixed point <= float_point - 1. Fixes that */ in nv10CalcArbitration()
968 // fifo empties. In that case we need to have an alternate clwm value in nv10CalcArbitration()
971 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; in nv10CalcArbitration()
978 /* Finally, a heuristic check when width == 64 bits */ in nv10CalcArbitration()
979 if(width == 1){ in nv10CalcArbitration()
1001 m1 = clwm + cbs - 1024; /* Amount of overfill */ in nv10CalcArbitration()
1009 fifo->valid = 0; in nv10CalcArbitration()
1018 min_mclk_extra--; in nv10CalcArbitration()
1022 fifo->valid = 0; in nv10CalcArbitration()
1027 min_mclk_extra--; in nv10CalcArbitration()
1031 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; in nv10CalcArbitration()
1034 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; in nv10CalcArbitration()
1037 fifo->video_lwm = 1024; fifo->video_burst_size = 512; in nv10CalcArbitration()
1053 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
1055 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1056 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv10UpdateArbitrationSettings()
1058 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1063 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? in nv10UpdateArbitrationSettings()
1065 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings()
1100 int domain = pci_domain_nr(pdev->bus); in nForceUpdateArbitrationSettings()
1110 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nForceUpdateArbitrationSettings()
1112 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nForceUpdateArbitrationSettings()
1169 if (chip->CrystalFreqKHz == 13500) in CalcVClock()
1172 highM = 13 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1177 highM = 14 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1180 highP = 4 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1184 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) in CalcVClock()
1188 N = (VClk << P) * M / chip->CrystalFreqKHz; in CalcVClock()
1190 Freq = (chip->CrystalFreqKHz * N / M) >> P; in CalcVClock()
1192 DeltaNew = Freq - VClk; in CalcVClock()
1194 DeltaNew = VClk - Freq; in CalcVClock()
1208 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ in CalcVClock()
1221 int width, in CalcStateExt() argument
1233 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ in CalcStateExt()
1234 state->width = width; in CalcStateExt()
1235 state->height = height; in CalcStateExt()
1241 return -EINVAL; in CalcStateExt()
1243 switch (chip->Architecture) in CalcStateExt()
1248 &(state->arbitration0), in CalcStateExt()
1249 &(state->arbitration1), in CalcStateExt()
1251 state->cursor0 = 0x00; in CalcStateExt()
1252 state->cursor1 = 0x78; in CalcStateExt()
1253 state->cursor2 = 0x00000000; in CalcStateExt()
1254 state->pllsel = 0x10010100; in CalcStateExt()
1255 state->config = ((width + 31)/32) in CalcStateExt()
1258 state->general = 0x00100100; in CalcStateExt()
1259 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; in CalcStateExt()
1264 &(state->arbitration0), in CalcStateExt()
1265 &(state->arbitration1), in CalcStateExt()
1267 state->cursor0 = 0x00; in CalcStateExt()
1268 state->cursor1 = 0xFC; in CalcStateExt()
1269 state->cursor2 = 0x00000000; in CalcStateExt()
1270 state->pllsel = 0x10000700; in CalcStateExt()
1271 state->config = 0x00001114; in CalcStateExt()
1272 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1273 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) || in CalcStateExt()
1279 (chip->Chipset == NV_CHIP_0x01F0)) in CalcStateExt()
1283 &(state->arbitration0), in CalcStateExt()
1284 &(state->arbitration1), in CalcStateExt()
1289 &(state->arbitration0), in CalcStateExt()
1290 &(state->arbitration1), in CalcStateExt()
1293 state->cursor0 = 0x80 | (chip->CursorStart >> 17); in CalcStateExt()
1294 state->cursor1 = (chip->CursorStart >> 11) << 2; in CalcStateExt()
1295 state->cursor2 = chip->CursorStart >> 24; in CalcStateExt()
1296 state->pllsel = 0x10000700; in CalcStateExt()
1297 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1298 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1299 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1305 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) in CalcStateExt()
1306 state->general |= 0x00000030; in CalcStateExt()
1308 state->vpll = (p << 16) | (n << 8) | m; in CalcStateExt()
1309 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; in CalcStateExt()
1310 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; in CalcStateExt()
1311 state->offset0 = in CalcStateExt()
1312 state->offset1 = in CalcStateExt()
1313 state->offset2 = in CalcStateExt()
1314 state->offset3 = 0; in CalcStateExt()
1315 state->pitch0 = in CalcStateExt()
1316 state->pitch1 = in CalcStateExt()
1317 state->pitch2 = in CalcStateExt()
1318 state->pitch3 = pixelDepth * width; in CalcStateExt()
1323 * Load fixed function state and pre-calculated/stored state.
1327 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1330 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1333 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1336 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1339 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1348 switch (chip->Architecture) in UpdateFifoState()
1351 LOAD_FIXED_STATE(nv4,FIFO); in UpdateFifoState()
1352 chip->Tri03 = NULL; in UpdateFifoState()
1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1362 LOAD_FIXED_STATE(nv10,FIFO); in UpdateFifoState()
1363 chip->Tri03 = NULL; in UpdateFifoState()
1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1381 switch (chip->Architecture) in LoadStateExt()
1387 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1391 switch (state->bpp) in LoadStateExt()
1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1403 chip->Tri03 = NULL; in LoadStateExt()
1409 chip->Tri03 = NULL; in LoadStateExt()
1413 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); in LoadStateExt()
1414 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); in LoadStateExt()
1415 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); in LoadStateExt()
1416 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); in LoadStateExt()
1417 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); in LoadStateExt()
1418 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); in LoadStateExt()
1419 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); in LoadStateExt()
1420 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); in LoadStateExt()
1421 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); in LoadStateExt()
1427 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1431 switch (state->bpp) in LoadStateExt()
1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1447 chip->Tri03 = NULL; in LoadStateExt()
1453 chip->Tri03 = NULL; in LoadStateExt()
1456 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1457 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1458 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1459 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1460 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1461 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1462 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1463 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1468 if(chip->twoHeads) { in LoadStateExt()
1469 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in LoadStateExt()
1470 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1471 chip->LockUnlock(chip, 0); in LoadStateExt()
1477 switch (state->bpp) in LoadStateExt()
1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1493 chip->Tri03 = NULL; in LoadStateExt()
1499 chip->Tri03 = NULL; in LoadStateExt()
1503 if(chip->Architecture == NV_ARCH_10) { in LoadStateExt()
1504 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1505 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1506 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1507 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1508 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1509 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1510 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1511 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1512 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); in LoadStateExt()
1514 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); in LoadStateExt()
1515 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); in LoadStateExt()
1516 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); in LoadStateExt()
1517 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); in LoadStateExt()
1518 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); in LoadStateExt()
1519 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); in LoadStateExt()
1520 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); in LoadStateExt()
1521 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); in LoadStateExt()
1522 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); in LoadStateExt()
1523 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); in LoadStateExt()
1524 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); in LoadStateExt()
1525 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); in LoadStateExt()
1527 if(chip->twoHeads) { in LoadStateExt()
1528 NV_WR32(chip->PCRTC0, 0x00000860, state->head); in LoadStateExt()
1529 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); in LoadStateExt()
1531 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1541 NV_WR32(chip->PFB, 0x00000240, 0); in LoadStateExt()
1542 NV_WR32(chip->PFB, 0x00000250, 0); in LoadStateExt()
1543 NV_WR32(chip->PFB, 0x00000260, 0); in LoadStateExt()
1544 NV_WR32(chip->PFB, 0x00000270, 0); in LoadStateExt()
1545 NV_WR32(chip->PFB, 0x00000280, 0); in LoadStateExt()
1546 NV_WR32(chip->PFB, 0x00000290, 0); in LoadStateExt()
1547 NV_WR32(chip->PFB, 0x000002A0, 0); in LoadStateExt()
1548 NV_WR32(chip->PFB, 0x000002B0, 0); in LoadStateExt()
1550 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); in LoadStateExt()
1551 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); in LoadStateExt()
1552 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); in LoadStateExt()
1553 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); in LoadStateExt()
1554 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); in LoadStateExt()
1555 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); in LoadStateExt()
1556 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); in LoadStateExt()
1557 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); in LoadStateExt()
1558 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); in LoadStateExt()
1559 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); in LoadStateExt()
1560 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); in LoadStateExt()
1561 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); in LoadStateExt()
1562 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); in LoadStateExt()
1563 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); in LoadStateExt()
1564 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); in LoadStateExt()
1565 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); in LoadStateExt()
1566 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); in LoadStateExt()
1567 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); in LoadStateExt()
1568 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); in LoadStateExt()
1569 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); in LoadStateExt()
1570 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); in LoadStateExt()
1571 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); in LoadStateExt()
1572 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); in LoadStateExt()
1573 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); in LoadStateExt()
1574 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); in LoadStateExt()
1575 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); in LoadStateExt()
1576 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); in LoadStateExt()
1577 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); in LoadStateExt()
1578 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); in LoadStateExt()
1579 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); in LoadStateExt()
1580 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); in LoadStateExt()
1581 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); in LoadStateExt()
1582 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); in LoadStateExt()
1583 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); in LoadStateExt()
1584 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1585 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); in LoadStateExt()
1586 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); in LoadStateExt()
1588 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1589 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1590 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1591 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); in LoadStateExt()
1593 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1594 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); in LoadStateExt()
1595 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); in LoadStateExt()
1596 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); in LoadStateExt()
1598 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1599 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); in LoadStateExt()
1601 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1602 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); in LoadStateExt()
1604 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1605 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); in LoadStateExt()
1607 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); in LoadStateExt()
1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); in LoadStateExt()
1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); in LoadStateExt()
1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); in LoadStateExt()
1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1624 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); in LoadStateExt()
1626 if(chip->flatPanel) { in LoadStateExt()
1627 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()
1628 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); in LoadStateExt()
1630 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()
1631 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); in LoadStateExt()
1634 VGA_WR08(chip->PCIO, 0x03D4, 0x53); in LoadStateExt()
1635 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1636 VGA_WR08(chip->PCIO, 0x03D4, 0x54); in LoadStateExt()
1637 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1638 VGA_WR08(chip->PCIO, 0x03D4, 0x21); in LoadStateExt()
1639 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); in LoadStateExt()
1642 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in LoadStateExt()
1643 VGA_WR08(chip->PCIO, 0x03D5, state->extra); in LoadStateExt()
1645 LOAD_FIXED_STATE(Riva,FIFO); in LoadStateExt()
1650 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in LoadStateExt()
1651 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); in LoadStateExt()
1652 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in LoadStateExt()
1653 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); in LoadStateExt()
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in LoadStateExt()
1655 VGA_WR08(chip->PCIO, 0x03D5, state->screen); in LoadStateExt()
1656 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in LoadStateExt()
1657 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); in LoadStateExt()
1658 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in LoadStateExt()
1659 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); in LoadStateExt()
1660 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in LoadStateExt()
1661 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); in LoadStateExt()
1662 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in LoadStateExt()
1663 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); in LoadStateExt()
1664 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in LoadStateExt()
1665 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); in LoadStateExt()
1666 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in LoadStateExt()
1667 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); in LoadStateExt()
1668 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in LoadStateExt()
1669 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); in LoadStateExt()
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in LoadStateExt()
1671 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); in LoadStateExt()
1673 if(!chip->flatPanel) { in LoadStateExt()
1674 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1675 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); in LoadStateExt()
1676 if(chip->twoHeads) in LoadStateExt()
1677 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); in LoadStateExt()
1679 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); in LoadStateExt()
1681 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); in LoadStateExt()
1686 NV_WR32(chip->PCRTC, 0x00000140, 0); in LoadStateExt()
1687 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1695 chip->CurrentState = state; in LoadStateExt()
1697 * Reset FIFO free and empty counts. in LoadStateExt()
1699 chip->FifoFreeCount = 0; in LoadStateExt()
1701 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); in LoadStateExt()
1712 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in UnloadStateExt()
1713 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1714 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in UnloadStateExt()
1715 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1716 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in UnloadStateExt()
1717 state->screen = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1718 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in UnloadStateExt()
1719 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1720 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in UnloadStateExt()
1721 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1722 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in UnloadStateExt()
1723 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1724 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in UnloadStateExt()
1725 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1726 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in UnloadStateExt()
1727 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1728 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in UnloadStateExt()
1729 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1730 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in UnloadStateExt()
1731 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1732 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in UnloadStateExt()
1733 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1734 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
1735 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); in UnloadStateExt()
1736 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); in UnloadStateExt()
1737 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); in UnloadStateExt()
1738 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); in UnloadStateExt()
1739 state->config = NV_RD32(chip->PFB, 0x00000200); in UnloadStateExt()
1740 switch (chip->Architecture) in UnloadStateExt()
1743 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); in UnloadStateExt()
1744 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); in UnloadStateExt()
1745 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); in UnloadStateExt()
1746 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); in UnloadStateExt()
1747 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); in UnloadStateExt()
1748 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); in UnloadStateExt()
1749 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); in UnloadStateExt()
1750 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); in UnloadStateExt()
1753 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1754 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1755 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1756 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1757 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1758 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1759 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1760 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1765 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1766 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1767 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1768 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1769 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1770 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1771 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1772 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1773 if(chip->twoHeads) { in UnloadStateExt()
1774 state->head = NV_RD32(chip->PCRTC0, 0x00000860); in UnloadStateExt()
1775 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); in UnloadStateExt()
1776 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in UnloadStateExt()
1777 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1779 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in UnloadStateExt()
1780 state->extra = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1781 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); in UnloadStateExt()
1783 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()
1784 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); in UnloadStateExt()
1786 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()
1787 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); in UnloadStateExt()
1798 NV_WR32(chip->PCRTC, 0x800, start); in SetStartAddress()
1814 chip->LockUnlock(chip, 0); in SetStartAddress3()
1818 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1820 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1822 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1823 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); in SetStartAddress3()
1824 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1825 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); in SetStartAddress3()
1829 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); in SetStartAddress3()
1830 VGA_WR08(chip->PCIO, 0x3C0, 0x13); in SetStartAddress3()
1831 VGA_WR08(chip->PCIO, 0x3C0, pan); in SetStartAddress3()
1841 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces2D()
1844 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv3SetSurfaces2D()
1845 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces2D()
1846 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv3SetSurfaces2D()
1847 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces2D()
1848 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces2D()
1858 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces2D()
1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv4SetSurfaces2D()
1861 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces2D()
1862 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv4SetSurfaces2D()
1863 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces2D()
1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces2D()
1874 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces2D()
1876 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv10SetSurfaces2D()
1877 NV_WR32(&Surface->Offset, 0, surf0); in nv10SetSurfaces2D()
1878 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv10SetSurfaces2D()
1879 NV_WR32(&Surface->Offset, 0, surf1); in nv10SetSurfaces2D()
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces2D()
1890 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces3D()
1893 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv3SetSurfaces3D()
1894 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces3D()
1895 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv3SetSurfaces3D()
1896 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces3D()
1897 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces3D()
1907 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces3D()
1909 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv4SetSurfaces3D()
1910 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces3D()
1911 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv4SetSurfaces3D()
1912 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces3D()
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces3D()
1923 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces3D()
1926 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); in nv10SetSurfaces3D()
1927 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); in nv10SetSurfaces3D()
1928 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); in nv10SetSurfaces3D()
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces3D()
1946 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) in nv3GetConfig()
1948 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
1949 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) in nv3GetConfig()
1954 chip->RamBandwidthKBytesPerSec = 800000; in nv3GetConfig()
1955 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) in nv3GetConfig()
1958 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
1961 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
1964 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1970 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
1971 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1979 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
1980 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv3GetConfig()
1983 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1986 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
1989 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
1993 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig()
1994 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); in nv3GetConfig()
1995 chip->VBlankBit = 0x00000100; in nv3GetConfig()
1996 chip->MaxVClockFreqKHz = 256000; in nv3GetConfig()
2000 chip->Busy = nv3Busy; in nv3GetConfig()
2001 chip->ShowHideCursor = ShowHideCursor; in nv3GetConfig()
2002 chip->LoadStateExt = LoadStateExt; in nv3GetConfig()
2003 chip->UnloadStateExt = UnloadStateExt; in nv3GetConfig()
2004 chip->SetStartAddress = SetStartAddress3; in nv3GetConfig()
2005 chip->SetSurfaces2D = nv3SetSurfaces2D; in nv3GetConfig()
2006 chip->SetSurfaces3D = nv3SetSurfaces3D; in nv3GetConfig()
2007 chip->LockUnlock = nv3LockUnlock; in nv3GetConfig()
2017 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) in nv4GetConfig()
2019 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 in nv4GetConfig()
2024 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv4GetConfig()
2027 chip->RamAmountKBytes = 1024 * 32; in nv4GetConfig()
2030 chip->RamAmountKBytes = 1024 * 4; in nv4GetConfig()
2033 chip->RamAmountKBytes = 1024 * 8; in nv4GetConfig()
2037 chip->RamAmountKBytes = 1024 * 16; in nv4GetConfig()
2041 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv4GetConfig()
2044 chip->RamBandwidthKBytesPerSec = 800000; in nv4GetConfig()
2047 chip->RamBandwidthKBytesPerSec = 1000000; in nv4GetConfig()
2050 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig()
2051 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); in nv4GetConfig()
2052 chip->VBlankBit = 0x00000001; in nv4GetConfig()
2053 chip->MaxVClockFreqKHz = 350000; in nv4GetConfig()
2057 chip->Busy = nv4Busy; in nv4GetConfig()
2058 chip->ShowHideCursor = ShowHideCursor; in nv4GetConfig()
2059 chip->LoadStateExt = LoadStateExt; in nv4GetConfig()
2060 chip->UnloadStateExt = UnloadStateExt; in nv4GetConfig()
2061 chip->SetStartAddress = SetStartAddress; in nv4GetConfig()
2062 chip->SetSurfaces2D = nv4SetSurfaces2D; in nv4GetConfig()
2063 chip->SetSurfaces3D = nv4SetSurfaces3D; in nv4GetConfig()
2064 chip->LockUnlock = nv4LockUnlock; in nv4GetConfig()
2074 int domain = pci_domain_nr(pdev->bus); in nv10GetConfig()
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
2080 NV_WR32(chip->PMC, 0x00000004, 0x01000001); in nv10GetConfig()
2090 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; in nv10GetConfig()
2095 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; in nv10GetConfig()
2097 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) in nv10GetConfig()
2100 chip->RamAmountKBytes = 1024 * 2; in nv10GetConfig()
2103 chip->RamAmountKBytes = 1024 * 4; in nv10GetConfig()
2106 chip->RamAmountKBytes = 1024 * 8; in nv10GetConfig()
2109 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2112 chip->RamAmountKBytes = 1024 * 32; in nv10GetConfig()
2115 chip->RamAmountKBytes = 1024 * 64; in nv10GetConfig()
2118 chip->RamAmountKBytes = 1024 * 128; in nv10GetConfig()
2121 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2125 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv10GetConfig()
2128 chip->RamBandwidthKBytesPerSec = 800000; in nv10GetConfig()
2131 chip->RamBandwidthKBytesPerSec = 1000000; in nv10GetConfig()
2134 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
2148 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
2149 chip->CrystalFreqKHz = 27000; in nv10GetConfig()
2155 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; in nv10GetConfig()
2156 chip->CURSOR = NULL; /* can't set this here */ in nv10GetConfig()
2157 chip->VBlankBit = 0x00000001; in nv10GetConfig()
2158 chip->MaxVClockFreqKHz = 350000; in nv10GetConfig()
2162 chip->Busy = nv10Busy; in nv10GetConfig()
2163 chip->ShowHideCursor = ShowHideCursor; in nv10GetConfig()
2164 chip->LoadStateExt = LoadStateExt; in nv10GetConfig()
2165 chip->UnloadStateExt = UnloadStateExt; in nv10GetConfig()
2166 chip->SetStartAddress = SetStartAddress; in nv10GetConfig()
2167 chip->SetSurfaces2D = nv10SetSurfaces2D; in nv10GetConfig()
2168 chip->SetSurfaces3D = nv10SetSurfaces3D; in nv10GetConfig()
2169 chip->LockUnlock = nv4LockUnlock; in nv10GetConfig()
2183 chip->twoHeads = TRUE; in nv10GetConfig()
2186 chip->twoHeads = FALSE; in nv10GetConfig()
2200 chip->Version = RIVA_SW_VERSION; in RivaGetConfig()
2204 switch (chip->Architecture) in RivaGetConfig()
2218 return (-1); in RivaGetConfig()
2220 chip->Chipset = chipset; in RivaGetConfig()
2222 * Fill in FIFO pointers. in RivaGetConfig()
2224 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); in RivaGetConfig()
2225 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); in RivaGetConfig()
2226 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); in RivaGetConfig()
2227 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); in RivaGetConfig()
2228 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); in RivaGetConfig()
2229 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); in RivaGetConfig()
2230 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); in RivaGetConfig()
2231 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in RivaGetConfig()