media/rc/ite-cir.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
11 /* FIFO sizes */
34 	/* hw-specific operation function pointers; most of these must be
35 	 * called while holding the spin lock, except for the TX FIFO length
50 	/* read bytes from RX FIFO; return read count */
53 	/* enable tx FIFO space available interrupt */
56 	/* disable tx FIFO space available interrupt */
59 	/* get number of full TX FIFO slots */
62 	/* put a byte to the TX FIFO */
98 	/* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135  * frequency A = (H - L) / (H + L). We can use this in order to honor the
136  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170  * Environment Control - Low Pin Count Input / Output
171  * (EC - LPC I/O)
192 #define IT87_RFOIE	0x04	/* receiver FIFO overrun interrupt enable */
202 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
210 #define IT87_FIFOTL	0x30	/* FIFO level threshold mask */
211 #define IT87_FIFOTL_DEFAULT 0x20	/* FIFO level threshold default
212 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 					 * 0x30 -> 25 */
215 #define IT87_FIFOCLR	0x80	/* FIFO clear bit */
218 #define IT87_TXMPW	0x07	/* transmitter modulation pulse width mask */
219 #define IT87_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
224 #define IT87_TXFBC	0x3f	/* transmitter FIFO byte count mask */
227 #define IT87_RXFBC	0x3f	/* receiver FIFO byte count mask */
228 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
236 #define IT87_II_RXFO	0x06	/* receiver FIFO overrun */
267 #define IT85_C0TFSR	0x0a	/* transmitter FIFO status register */
268 #define IT85_C0RFSR	0x0b	/* receiver FIFO status register */
277 #define IT85_FIFOCLR	0x02	/* FIFO clear bit */
278 #define IT85_FIFOTL	0x0c	/* FIFO level threshold mask */
279 #define IT85_FIFOTL_DEFAULT 0x08	/* FIFO level threshold default
280 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 					 * 0x0c -> 25 */
288 #define IT85_RFOIE	0x04	/* RX FIFO overrun interrupt enable */
294 #define IT85_RFOI	0x04	/* receiver FIFO overrun interrupt */
309 #define IT85_TXMPW	0x07	/* transmitter modulation pulse width mask */
310 #define IT85_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
325 #define IT85_TXFBC	0x3f	/* transmitter FIFO count mask */
328 #define IT85_RXFBC	0x3f	/* receiver FIFO count mask */
329 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
349  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350  * selectable by a single bank-select bit that's mapped onto both banks. The
353  * reserved high-order bit are placed at the same offset in both banks in
368 #define IT8708_C0RFSR	0x04	/* receiver FIFO status register */
370 #define IT8708_C0TFSR	0x06	/* transmitter FIFO status register */
408  * a specific firmware running on the IT8512's embedded micro-controller.
409  * In addition of the embedded micro-controller, the IT8512 chip contains a
412  * micro-controller. The CIR module is only accessible by the
413  * micro-controller.
415  * The battery-backed SRAM module is accessible by the host CPU and the
416  * micro-controller. So one of the MC's firmware role is to act as a bridge
420  * communication protocol is not, so it was reverse-engineered.
434 #define IT8709_RFSR	0x1f	/* receiver FIFO status register */
435 #define IT8709_FIFO	0x20	/* start of in RAM RX FIFO copy */