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/linux-6.12.1/drivers/watchdog/
Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
31 #include <linux/clk.h>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
43 * something quite higher than 100 (or we need a proper high-res timer
46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
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/linux-6.12.1/drivers/clk/
Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
31 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
33 return readl_relaxed(csr); in xgene_clk_read()
36 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
38 writel_relaxed(data, csr); in xgene_clk_write()
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 Registers(CSR) module represents a set of miscellaneous registers of a
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
19 should consider all subnodes of the CSR module as separate child devices.
23 pattern: "^syscon@[0-9a-f]+$"
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/linux-6.12.1/drivers/spi/
Dspi-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
226 readl_relaxed((port)->regs + SPI_##reg)
228 writel_relaxed((value), (port)->regs + SPI_##reg)
230 writew_relaxed((value), (port)->regs + SPI_##reg)
258 struct clk *clk; member
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/linux-6.12.1/drivers/net/wireless/ralink/rt2x00/
Drt2x00soc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2004 - 2009 Felix Fietkau <nbd@openwrt.org>
25 kfree(rt2x00dev->rf); in rt2x00soc_free_reg()
26 rt2x00dev->rf = NULL; in rt2x00soc_free_reg()
28 kfree(rt2x00dev->eeprom); in rt2x00soc_free_reg()
29 rt2x00dev->eeprom = NULL; in rt2x00soc_free_reg()
31 iounmap(rt2x00dev->csr.base); in rt2x00soc_free_reg()
36 struct platform_device *pdev = to_platform_device(rt2x00dev->dev); in rt2x00soc_alloc_reg()
41 return -ENODEV; in rt2x00soc_alloc_reg()
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/linux-6.12.1/drivers/net/pcs/
Dpcs-xpcs-plat.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
15 #include <linux/pcs/pcs-xpcs.h>
22 #include "pcs-xpcs.h"
33 struct clk *cclk;
41 static u16 xpcs_mmio_addr_page(ptrdiff_t csr) in xpcs_mmio_addr_page() argument
43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
46 static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr) in xpcs_mmio_addr_offset() argument
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
54 ptrdiff_t csr, ofs; in xpcs_mmio_read_reg_indirect() local
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/linux-6.12.1/drivers/dma/stm32/
Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
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/linux-6.12.1/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
13 #include <linux/clk.h>
15 #include <linux/dma-mapping.h>
27 /* X-Gene DMA ring csr registers and bit definations */
44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
46 ((m) &= (~BIT(31 - (v))))
77 /* X-Gene DMA device csr registers and bit definitions */
106 /* X-Gene SoC EFUSE csr register and bit defination */
110 /* X-Gene DMA Descriptor format */
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Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
7 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
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Dtegra20-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
9 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
40 /* CSR register */
103 * on-flight burst and update DMA status register.
132 u32 csr; member
144 * sub-transfer as per requester details and hw support.
201 /* Channel-slave specific configuration */
213 struct clk *dma_clk;
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/linux-6.12.1/drivers/iio/adc/
Dstm32-adc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
13 #include <linux/clk.h>
30 #include "stm32-adc-core.h"
46 * struct stm32_adc_common_regs - stm32 common registers
47 * @csr: common status register offset
49 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
50 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
55 u32 csr; member
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/linux-6.12.1/drivers/net/ethernet/qualcomm/emac/
Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
18 #include "emac-mac.h"
19 #include "emac-phy.h"
20 #include "emac-sgmii.h"
84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
100 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
101 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
109 irq->mask |= rx_q->intr; in emac_napi_rtx()
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/linux-6.12.1/drivers/clk/imx/
Dclk-imx95-blk-ctl.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
33 struct clk *clk_apb;
282 struct device *dev = &pdev->dev; in imx95_bc_probe()
292 return -ENOMEM; in imx95_bc_probe()
293 bc->dev = dev; in imx95_bc_probe()
294 dev_set_drvdata(&pdev->dev, bc); in imx95_bc_probe()
296 spin_lock_init(&bc->lock); in imx95_bc_probe()
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Dclk-pllv4.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk-provider.h>
17 #include "clk.h"
62 u32 csr; in clk_pllv4_wait_lock() local
64 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock()
65 csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US); in clk_pllv4_wait_lock()
72 if (readl_relaxed(pll->base) & PLL_EN) in clk_pllv4_is_prepared()
85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
89 mfn = readl_relaxed(pll->base + pll->num_offset); in clk_pllv4_recalc_rate()
90 mfd = readl_relaxed(pll->base + pll->denom_offset); in clk_pllv4_recalc_rate()
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
24 by Control and Status Registers(CSR) module in the SoC. The CSR
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
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Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
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/linux-6.12.1/drivers/pci/controller/
Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
9 #include <linux/clk.h>
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
64 struct clk *clk; member
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
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/linux-6.12.1/drivers/mmc/host/
Dwbsd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/wbsd.c - Winbond W83L51xD SD/MMC driver
5 * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.
12 * - FIFO size field in FSR is always zero.
14 * - FIFO interrupts tend not to work as they should. Interrupts are
17 * - On APIC systems the FIFO empty interrupt is sometimes lost.
26 #include <linux/dma-mapping.h>
86 BUG_ON(host->config == 0); in wbsd_unlock_config()
88 outb(host->unlock_code, host->config); in wbsd_unlock_config()
89 outb(host->unlock_code, host->config); in wbsd_unlock_config()
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/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
26 Status Registers (CSR) module, are accessed through the bus.
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
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/linux-6.12.1/drivers/tty/serial/
Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk.h>
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
225 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_read()
228 ret = readb(port->membase + (reg << port->regshift)); in sccnxp_read()
230 ndelay(s->chip->trwd); in sccnxp_read()
237 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_write()
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/linux-6.12.1/drivers/i2c/busses/
Di2c-octeon-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <linux/clk.h>
8 #include <linux/i2c-smbus.h>
42 #define TWSI_CTL_STA 0x20 /* Controller-mode start, HW clears when done */
43 #define TWSI_CTL_STP 0x10 /* Controller-mode stop, HW clears when done */
101 #define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi)
102 #define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int)
103 #define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext)
104 #define OCTEON_REG_MODE(x) ((x)->roff.mode)
118 struct clk *clk; member
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ipq806x.c23 #include <linux/clk.h>
85 (0x13c + (4 * (x - 2))))
111 struct clk *core_clk;
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
135 return -EINVAL; in get_clk_div_sgmii()
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
161 return -EINVAL; in get_clk_div_rgmii()
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
178 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
179 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
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/linux-6.12.1/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
65 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
124 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra30_boot_secondary()
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/linux-6.12.1/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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