bindings/phy/fsl%2Cimx8qm-lvds-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Liu Ying <victor.liu@nxp.com>
15   groups of four data lanes of LVDS data streams. A phase-locked
24   by Control and Status Registers(CSR) module in the SoC. The CSR
30       - fsl,imx8qm-lvds-phy
31       - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33   "#phy-cells":
42   power-domains:
46   - compatible
47   - "#phy-cells"
48   - clocks
49   - power-domains
54   - |
55     #include <dt-bindings/firmware/imx/rsrc.h>
57         compatible = "fsl,imx8qm-lvds-phy";
58         #phy-cells = <1>;
59         clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
60         power-domains = <&pd IMX_SC_R_LVDS_0>;