Lines Matching +full:clk +full:- +full:csr
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
9 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
40 /* CSR register */
103 * on-flight burst and update DMA status register.
132 u32 csr; member
144 * sub-transfer as per requester details and hw support.
201 /* Channel-slave specific configuration */
213 struct clk *dma_clk;
232 writel(val, tdma->base_addr + reg); in tdma_write()
238 writel(val, tdc->chan_addr + reg); in tdc_write()
243 return readl(tdc->chan_addr + reg); in tdc_read()
259 return &tdc->dma_chan.dev->device; in tdc2dev()
270 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_get()
273 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_desc_get()
274 if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) { in tegra_dma_desc_get()
275 list_del(&dma_desc->node); in tegra_dma_desc_get()
276 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
277 dma_desc->txd.flags = 0; in tegra_dma_desc_get()
282 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
289 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan); in tegra_dma_desc_get()
290 dma_desc->txd.tx_submit = tegra_dma_tx_submit; in tegra_dma_desc_get()
291 dma_desc->txd.flags = 0; in tegra_dma_desc_get()
301 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_put()
302 if (!list_empty(&dma_desc->tx_list)) in tegra_dma_desc_put()
303 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req); in tegra_dma_desc_put()
304 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_desc_put()
305 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_put()
314 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_sg_req_get()
315 if (!list_empty(&tdc->free_sg_req)) { in tegra_dma_sg_req_get()
316 sg_req = list_first_entry(&tdc->free_sg_req, typeof(*sg_req), in tegra_dma_sg_req_get()
318 list_del(&sg_req->node); in tegra_dma_sg_req_get()
319 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
322 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
334 if (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_slave_config()
336 return -EBUSY; in tegra_dma_slave_config()
339 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
340 tdc->config_init = true; in tegra_dma_slave_config()
348 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_pause()
350 spin_lock(&tdma->global_lock); in tegra_dma_global_pause()
352 if (tdc->tdma->global_pause_count == 0) { in tegra_dma_global_pause()
358 tdc->tdma->global_pause_count++; in tegra_dma_global_pause()
360 spin_unlock(&tdma->global_lock); in tegra_dma_global_pause()
365 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_resume()
367 spin_lock(&tdma->global_lock); in tegra_dma_global_resume()
369 if (WARN_ON(tdc->tdma->global_pause_count == 0)) in tegra_dma_global_resume()
372 if (--tdc->tdma->global_pause_count == 0) in tegra_dma_global_resume()
377 spin_unlock(&tdma->global_lock); in tegra_dma_global_resume()
383 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_pause()
385 if (tdma->chip_data->support_channel_pause) { in tegra_dma_pause()
397 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_resume()
399 if (tdma->chip_data->support_channel_pause) in tegra_dma_resume()
407 u32 csr, status; in tegra_dma_stop() local
410 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_stop()
411 csr &= ~TEGRA_APBDMA_CSR_IE_EOC; in tegra_dma_stop()
412 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
415 csr &= ~TEGRA_APBDMA_CSR_ENB; in tegra_dma_stop()
416 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
424 tdc->busy = false; in tegra_dma_stop()
430 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs; in tegra_dma_start()
432 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
433 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); in tegra_dma_start()
434 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); in tegra_dma_start()
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); in tegra_dma_start()
436 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); in tegra_dma_start()
437 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_start()
438 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
442 ch_regs->csr | TEGRA_APBDMA_CSR_ENB); in tegra_dma_start()
476 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); in tegra_dma_configure_for_next()
477 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr); in tegra_dma_configure_for_next()
478 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_configure_for_next()
480 nsg_req->ch_regs.wcount); in tegra_dma_configure_for_next()
482 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB); in tegra_dma_configure_for_next()
483 nsg_req->configured = true; in tegra_dma_configure_for_next()
484 nsg_req->words_xferred = 0; in tegra_dma_configure_for_next()
493 sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node); in tdc_start_head_req()
495 sg_req->configured = true; in tdc_start_head_req()
496 sg_req->words_xferred = 0; in tdc_start_head_req()
497 tdc->busy = true; in tdc_start_head_req()
504 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in tdc_configure_next_head_desc()
505 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) { in tdc_configure_next_head_desc()
506 hnsgreq = list_first_entry(&hsgreq->node, typeof(*hnsgreq), in tdc_configure_next_head_desc()
517 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4; in get_current_xferred_count()
525 while (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_abort_all()
526 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_abort_all()
528 list_move_tail(&sgreq->node, &tdc->free_sg_req); in tegra_dma_abort_all()
529 if (sgreq->last_sg) { in tegra_dma_abort_all()
530 dma_desc = sgreq->dma_desc; in tegra_dma_abort_all()
531 dma_desc->dma_status = DMA_ERROR; in tegra_dma_abort_all()
532 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_abort_all()
535 if (!dma_desc->cb_count) in tegra_dma_abort_all()
536 list_add_tail(&dma_desc->cb_node, in tegra_dma_abort_all()
537 &tdc->cb_desc); in tegra_dma_abort_all()
538 dma_desc->cb_count++; in tegra_dma_abort_all()
541 tdc->isr_handler = NULL; in tegra_dma_abort_all()
554 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in handle_continuous_head_request()
555 if (!hsgreq->configured) { in handle_continuous_head_request()
557 pm_runtime_put(tdc->tdma->dev); in handle_continuous_head_request()
576 tdc->busy = false; in handle_once_dma_done()
577 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_once_dma_done()
578 dma_desc = sgreq->dma_desc; in handle_once_dma_done()
579 dma_desc->bytes_transferred += sgreq->req_len; in handle_once_dma_done()
581 list_del(&sgreq->node); in handle_once_dma_done()
582 if (sgreq->last_sg) { in handle_once_dma_done()
583 dma_desc->dma_status = DMA_COMPLETE; in handle_once_dma_done()
584 dma_cookie_complete(&dma_desc->txd); in handle_once_dma_done()
585 if (!dma_desc->cb_count) in handle_once_dma_done()
586 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_once_dma_done()
587 dma_desc->cb_count++; in handle_once_dma_done()
588 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in handle_once_dma_done()
590 list_add_tail(&sgreq->node, &tdc->free_sg_req); in handle_once_dma_done()
596 if (list_empty(&tdc->pending_sg_req)) { in handle_once_dma_done()
597 pm_runtime_put(tdc->tdma->dev); in handle_once_dma_done()
611 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_cont_sngl_cycle_dma_done()
612 dma_desc = sgreq->dma_desc; in handle_cont_sngl_cycle_dma_done()
614 dma_desc->bytes_transferred = in handle_cont_sngl_cycle_dma_done()
615 (dma_desc->bytes_transferred + sgreq->req_len) % in handle_cont_sngl_cycle_dma_done()
616 dma_desc->bytes_requested; in handle_cont_sngl_cycle_dma_done()
619 if (!dma_desc->cb_count) in handle_cont_sngl_cycle_dma_done()
620 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_cont_sngl_cycle_dma_done()
621 dma_desc->cb_count++; in handle_cont_sngl_cycle_dma_done()
623 sgreq->words_xferred = 0; in handle_cont_sngl_cycle_dma_done()
626 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) { in handle_cont_sngl_cycle_dma_done()
627 list_move_tail(&sgreq->node, &tdc->pending_sg_req); in handle_cont_sngl_cycle_dma_done()
628 sgreq->configured = false; in handle_cont_sngl_cycle_dma_done()
631 dma_desc->dma_status = DMA_ERROR; in handle_cont_sngl_cycle_dma_done()
643 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
644 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_tasklet()
645 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_tasklet()
647 list_del(&dma_desc->cb_node); in tegra_dma_tasklet()
648 dmaengine_desc_get_callback(&dma_desc->txd, &cb); in tegra_dma_tasklet()
649 cb_count = dma_desc->cb_count; in tegra_dma_tasklet()
650 dma_desc->cb_count = 0; in tegra_dma_tasklet()
651 trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count, in tegra_dma_tasklet()
653 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
654 while (cb_count--) in tegra_dma_tasklet()
656 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
658 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
666 spin_lock(&tdc->lock); in tegra_dma_isr()
668 trace_tegra_dma_isr(&tdc->dma_chan, irq); in tegra_dma_isr()
672 tdc->isr_handler(tdc, false); in tegra_dma_isr()
673 tasklet_schedule(&tdc->tasklet); in tegra_dma_isr()
674 wake_up_all(&tdc->wq); in tegra_dma_isr()
675 spin_unlock(&tdc->lock); in tegra_dma_isr()
679 spin_unlock(&tdc->lock); in tegra_dma_isr()
689 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan); in tegra_dma_tx_submit()
693 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_submit()
694 dma_desc->dma_status = DMA_IN_PROGRESS; in tegra_dma_tx_submit()
695 cookie = dma_cookie_assign(&dma_desc->txd); in tegra_dma_tx_submit()
696 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); in tegra_dma_tx_submit()
697 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_submit()
708 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_issue_pending()
709 if (list_empty(&tdc->pending_sg_req)) { in tegra_dma_issue_pending()
713 if (!tdc->busy) { in tegra_dma_issue_pending()
714 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_issue_pending()
723 if (tdc->cyclic) { in tegra_dma_issue_pending()
733 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_issue_pending()
745 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_terminate_all()
747 if (!tdc->busy) in tegra_dma_terminate_all()
756 tdc->isr_handler(tdc, true); in tegra_dma_terminate_all()
759 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_terminate_all()
764 was_busy = tdc->busy; in tegra_dma_terminate_all()
767 if (!list_empty(&tdc->pending_sg_req) && was_busy) { in tegra_dma_terminate_all()
768 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_terminate_all()
770 sgreq->dma_desc->bytes_transferred += in tegra_dma_terminate_all()
775 pm_runtime_put(tdc->tdma->dev); in tegra_dma_terminate_all()
776 wake_up_all(&tdc->wq); in tegra_dma_terminate_all()
781 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_terminate_all()
782 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_terminate_all()
784 list_del(&dma_desc->cb_node); in tegra_dma_terminate_all()
785 dma_desc->cb_count = 0; in tegra_dma_terminate_all()
787 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_terminate_all()
797 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
799 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
809 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_synchronize()
820 wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc)); in tegra_dma_synchronize()
822 tasklet_kill(&tdc->tasklet); in tegra_dma_synchronize()
824 pm_runtime_put(tdc->tdma->dev); in tegra_dma_synchronize()
832 if (!list_is_first(&sg_req->node, &tdc->pending_sg_req)) in tegra_dma_sg_bytes_xferred()
835 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
840 if (!tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
844 return sg_req->req_len; in tegra_dma_sg_bytes_xferred()
863 if (sg_req->words_xferred) in tegra_dma_sg_bytes_xferred()
864 wcount = sg_req->req_len - 4; in tegra_dma_sg_bytes_xferred()
866 } else if (wcount < sg_req->words_xferred) { in tegra_dma_sg_bytes_xferred()
868 * This case will never happen for a non-cyclic transfer. in tegra_dma_sg_bytes_xferred()
878 wcount = sg_req->req_len - 4; in tegra_dma_sg_bytes_xferred()
880 sg_req->words_xferred = wcount; in tegra_dma_sg_bytes_xferred()
902 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_status()
905 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_tx_status()
906 if (dma_desc->txd.cookie == cookie) { in tegra_dma_tx_status()
907 ret = dma_desc->dma_status; in tegra_dma_tx_status()
913 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { in tegra_dma_tx_status()
914 dma_desc = sg_req->dma_desc; in tegra_dma_tx_status()
915 if (dma_desc->txd.cookie == cookie) { in tegra_dma_tx_status()
917 ret = dma_desc->dma_status; in tegra_dma_tx_status()
927 residual = dma_desc->bytes_requested - in tegra_dma_tx_status()
928 ((dma_desc->bytes_transferred + bytes) % in tegra_dma_tx_status()
929 dma_desc->bytes_requested); in tegra_dma_tx_status()
933 trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate); in tegra_dma_tx_status()
934 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
993 u32 *csr, in get_transfer_param() argument
999 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
1000 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
1001 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
1002 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
1003 *csr = TEGRA_APBDMA_CSR_DIR; in get_transfer_param()
1007 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
1008 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
1009 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
1010 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
1011 *csr = 0; in get_transfer_param()
1019 return -EINVAL; in get_transfer_param()
1026 u32 len_field = (len - 4) & 0xFFFC; in tegra_dma_prep_wcount()
1028 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_prep_wcount()
1029 ch_regs->wcount = len_field; in tegra_dma_prep_wcount()
1031 ch_regs->csr |= len_field; in tegra_dma_prep_wcount()
1044 u32 csr, ahb_seq, apb_ptr, apb_seq; in tegra_dma_prep_slave_sg() local
1052 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1061 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_slave_sg()
1072 csr |= TEGRA_APBDMA_CSR_ONCE; in tegra_dma_prep_slave_sg()
1074 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_slave_sg()
1075 csr |= TEGRA_APBDMA_CSR_FLOW; in tegra_dma_prep_slave_sg()
1076 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_slave_sg()
1080 csr |= TEGRA_APBDMA_CSR_IE_EOC; in tegra_dma_prep_slave_sg()
1093 INIT_LIST_HEAD(&dma_desc->tx_list); in tegra_dma_prep_slave_sg()
1094 INIT_LIST_HEAD(&dma_desc->cb_node); in tegra_dma_prep_slave_sg()
1095 dma_desc->cb_count = 0; in tegra_dma_prep_slave_sg()
1096 dma_desc->bytes_requested = 0; in tegra_dma_prep_slave_sg()
1097 dma_desc->bytes_transferred = 0; in tegra_dma_prep_slave_sg()
1098 dma_desc->dma_status = DMA_IN_PROGRESS; in tegra_dma_prep_slave_sg()
1108 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_slave_sg()
1117 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_slave_sg()
1123 dma_desc->bytes_requested += len; in tegra_dma_prep_slave_sg()
1125 sg_req->ch_regs.apb_ptr = apb_ptr; in tegra_dma_prep_slave_sg()
1126 sg_req->ch_regs.ahb_ptr = mem; in tegra_dma_prep_slave_sg()
1127 sg_req->ch_regs.csr = csr; in tegra_dma_prep_slave_sg()
1128 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_slave_sg()
1129 sg_req->ch_regs.apb_seq = apb_seq; in tegra_dma_prep_slave_sg()
1130 sg_req->ch_regs.ahb_seq = ahb_seq; in tegra_dma_prep_slave_sg()
1131 sg_req->configured = false; in tegra_dma_prep_slave_sg()
1132 sg_req->last_sg = false; in tegra_dma_prep_slave_sg()
1133 sg_req->dma_desc = dma_desc; in tegra_dma_prep_slave_sg()
1134 sg_req->req_len = len; in tegra_dma_prep_slave_sg()
1136 list_add_tail(&sg_req->node, &dma_desc->tx_list); in tegra_dma_prep_slave_sg()
1138 sg_req->last_sg = true; in tegra_dma_prep_slave_sg()
1140 dma_desc->txd.flags = DMA_CTRL_ACK; in tegra_dma_prep_slave_sg()
1146 if (!tdc->isr_handler) { in tegra_dma_prep_slave_sg()
1147 tdc->isr_handler = handle_once_dma_done; in tegra_dma_prep_slave_sg()
1148 tdc->cyclic = false; in tegra_dma_prep_slave_sg()
1150 if (tdc->cyclic) { in tegra_dma_prep_slave_sg()
1157 return &dma_desc->txd; in tegra_dma_prep_slave_sg()
1169 u32 csr, ahb_seq, apb_ptr, apb_seq; in tegra_dma_prep_dma_cyclic() local
1181 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1192 if (tdc->busy) { in tegra_dma_prep_dma_cyclic()
1208 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_dma_cyclic()
1213 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_dma_cyclic()
1222 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_dma_cyclic()
1223 csr |= TEGRA_APBDMA_CSR_FLOW; in tegra_dma_prep_dma_cyclic()
1224 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_dma_cyclic()
1228 csr |= TEGRA_APBDMA_CSR_IE_EOC; in tegra_dma_prep_dma_cyclic()
1242 INIT_LIST_HEAD(&dma_desc->tx_list); in tegra_dma_prep_dma_cyclic()
1243 INIT_LIST_HEAD(&dma_desc->cb_node); in tegra_dma_prep_dma_cyclic()
1244 dma_desc->cb_count = 0; in tegra_dma_prep_dma_cyclic()
1246 dma_desc->bytes_transferred = 0; in tegra_dma_prep_dma_cyclic()
1247 dma_desc->bytes_requested = buf_len; in tegra_dma_prep_dma_cyclic()
1254 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_dma_cyclic()
1260 sg_req->ch_regs.apb_ptr = apb_ptr; in tegra_dma_prep_dma_cyclic()
1261 sg_req->ch_regs.ahb_ptr = mem; in tegra_dma_prep_dma_cyclic()
1262 sg_req->ch_regs.csr = csr; in tegra_dma_prep_dma_cyclic()
1263 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_dma_cyclic()
1264 sg_req->ch_regs.apb_seq = apb_seq; in tegra_dma_prep_dma_cyclic()
1265 sg_req->ch_regs.ahb_seq = ahb_seq; in tegra_dma_prep_dma_cyclic()
1266 sg_req->configured = false; in tegra_dma_prep_dma_cyclic()
1267 sg_req->last_sg = false; in tegra_dma_prep_dma_cyclic()
1268 sg_req->dma_desc = dma_desc; in tegra_dma_prep_dma_cyclic()
1269 sg_req->req_len = len; in tegra_dma_prep_dma_cyclic()
1271 list_add_tail(&sg_req->node, &dma_desc->tx_list); in tegra_dma_prep_dma_cyclic()
1272 remain_len -= len; in tegra_dma_prep_dma_cyclic()
1275 sg_req->last_sg = true; in tegra_dma_prep_dma_cyclic()
1277 dma_desc->txd.flags = DMA_CTRL_ACK; in tegra_dma_prep_dma_cyclic()
1283 if (!tdc->isr_handler) { in tegra_dma_prep_dma_cyclic()
1284 tdc->isr_handler = handle_cont_sngl_cycle_dma_done; in tegra_dma_prep_dma_cyclic()
1285 tdc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1287 if (!tdc->cyclic) { in tegra_dma_prep_dma_cyclic()
1294 return &dma_desc->txd; in tegra_dma_prep_dma_cyclic()
1301 dma_cookie_init(&tdc->dma_chan); in tegra_dma_alloc_chan_resources()
1317 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1320 tasklet_kill(&tdc->tasklet); in tegra_dma_free_chan_resources()
1322 list_splice_init(&tdc->pending_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1323 list_splice_init(&tdc->free_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1324 list_splice_init(&tdc->free_dma_desc, &dma_desc_list); in tegra_dma_free_chan_resources()
1325 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_free_chan_resources()
1326 tdc->config_init = false; in tegra_dma_free_chan_resources()
1327 tdc->isr_handler = NULL; in tegra_dma_free_chan_resources()
1332 list_del(&dma_desc->node); in tegra_dma_free_chan_resources()
1338 list_del(&sg_req->node); in tegra_dma_free_chan_resources()
1342 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_free_chan_resources()
1348 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
1352 if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) { in tegra_dma_of_xlate()
1353 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]); in tegra_dma_of_xlate()
1357 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1362 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1407 err = reset_control_assert(tdma->rst); in tegra_dma_init_hw()
1409 dev_err(tdma->dev, "failed to assert reset: %d\n", err); in tegra_dma_init_hw()
1413 err = clk_enable(tdma->dma_clk); in tegra_dma_init_hw()
1415 dev_err(tdma->dev, "failed to enable clk: %d\n", err); in tegra_dma_init_hw()
1421 reset_control_deassert(tdma->rst); in tegra_dma_init_hw()
1428 clk_disable(tdma->dma_clk); in tegra_dma_init_hw()
1441 cdata = of_device_get_match_data(&pdev->dev); in tegra_dma_probe()
1442 size = struct_size(tdma, channels, cdata->nr_channels); in tegra_dma_probe()
1444 tdma = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); in tegra_dma_probe()
1446 return -ENOMEM; in tegra_dma_probe()
1448 tdma->dev = &pdev->dev; in tegra_dma_probe()
1449 tdma->chip_data = cdata; in tegra_dma_probe()
1452 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_dma_probe()
1453 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1454 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1456 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL); in tegra_dma_probe()
1457 if (IS_ERR(tdma->dma_clk)) { in tegra_dma_probe()
1458 dev_err(&pdev->dev, "Error: Missing controller clock\n"); in tegra_dma_probe()
1459 return PTR_ERR(tdma->dma_clk); in tegra_dma_probe()
1462 tdma->rst = devm_reset_control_get(&pdev->dev, "dma"); in tegra_dma_probe()
1463 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1464 dev_err(&pdev->dev, "Error: Missing reset\n"); in tegra_dma_probe()
1465 return PTR_ERR(tdma->rst); in tegra_dma_probe()
1468 spin_lock_init(&tdma->global_lock); in tegra_dma_probe()
1470 ret = clk_prepare(tdma->dma_clk); in tegra_dma_probe()
1478 pm_runtime_irq_safe(&pdev->dev); in tegra_dma_probe()
1479 pm_runtime_enable(&pdev->dev); in tegra_dma_probe()
1481 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1482 for (i = 0; i < cdata->nr_channels; i++) { in tegra_dma_probe()
1483 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1486 tdc->chan_addr = tdma->base_addr + in tegra_dma_probe()
1488 (i * cdata->channel_reg_size); in tegra_dma_probe()
1496 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i); in tegra_dma_probe()
1497 ret = devm_request_irq(&pdev->dev, irq, tegra_dma_isr, 0, in tegra_dma_probe()
1498 tdc->name, tdc); in tegra_dma_probe()
1500 dev_err(&pdev->dev, in tegra_dma_probe()
1506 tdc->dma_chan.device = &tdma->dma_dev; in tegra_dma_probe()
1507 dma_cookie_init(&tdc->dma_chan); in tegra_dma_probe()
1508 list_add_tail(&tdc->dma_chan.device_node, in tegra_dma_probe()
1509 &tdma->dma_dev.channels); in tegra_dma_probe()
1510 tdc->tdma = tdma; in tegra_dma_probe()
1511 tdc->id = i; in tegra_dma_probe()
1512 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_probe()
1514 tasklet_setup(&tdc->tasklet, tegra_dma_tasklet); in tegra_dma_probe()
1515 spin_lock_init(&tdc->lock); in tegra_dma_probe()
1516 init_waitqueue_head(&tdc->wq); in tegra_dma_probe()
1518 INIT_LIST_HEAD(&tdc->pending_sg_req); in tegra_dma_probe()
1519 INIT_LIST_HEAD(&tdc->free_sg_req); in tegra_dma_probe()
1520 INIT_LIST_HEAD(&tdc->free_dma_desc); in tegra_dma_probe()
1521 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_probe()
1524 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1525 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1526 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1528 tdma->global_pause_count = 0; in tegra_dma_probe()
1529 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1530 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1532 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1534 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1535 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1536 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in tegra_dma_probe()
1540 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in tegra_dma_probe()
1544 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_dma_probe()
1545 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in tegra_dma_probe()
1546 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1547 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1548 tdma->dma_dev.device_synchronize = tegra_dma_synchronize; in tegra_dma_probe()
1549 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1550 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1552 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1554 dev_err(&pdev->dev, in tegra_dma_probe()
1559 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_dma_probe()
1562 dev_err(&pdev->dev, in tegra_dma_probe()
1567 dev_info(&pdev->dev, "Tegra20 APB DMA driver registered %u channels\n", in tegra_dma_probe()
1568 cdata->nr_channels); in tegra_dma_probe()
1573 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1576 pm_runtime_disable(&pdev->dev); in tegra_dma_probe()
1579 clk_unprepare(tdma->dma_clk); in tegra_dma_probe()
1588 of_dma_controller_free(pdev->dev.of_node); in tegra_dma_remove()
1589 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1590 pm_runtime_disable(&pdev->dev); in tegra_dma_remove()
1591 clk_unprepare(tdma->dma_clk); in tegra_dma_remove()
1598 clk_disable(tdma->dma_clk); in tegra_dma_runtime_suspend()
1607 return clk_enable(tdma->dma_clk); in tegra_dma_runtime_resume()
1617 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_dev_suspend()
1618 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_dev_suspend()
1620 tasklet_kill(&tdc->tasklet); in tegra_dma_dev_suspend()
1622 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_dev_suspend()
1623 busy = tdc->busy; in tegra_dma_dev_suspend()
1624 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_dev_suspend()
1627 dev_err(tdma->dev, "channel %u busy\n", i); in tegra_dma_dev_suspend()
1628 return -EBUSY; in tegra_dma_dev_suspend()
1655 .compatible = "nvidia,tegra148-apbdma",
1658 .compatible = "nvidia,tegra114-apbdma",
1661 .compatible = "nvidia,tegra30-apbdma",
1664 .compatible = "nvidia,tegra20-apbdma",
1673 .name = "tegra-apbdma",