Lines Matching +full:clk +full:- +full:csr
1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
9 #include <linux/clk.h>
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
64 struct clk *clk; member
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
95 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
106 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
107 return port->cfg_base + AXI_EP_CFG_ACCESS; in xgene_pcie_get_cfg_base()
109 return port->cfg_base; in xgene_pcie_get_cfg_base()
122 b = bus->number; in xgene_pcie_set_rtdid_reg()
135 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
175 * we read the Vendor and Device ID of a non-existent device, the in xgene_pcie_config_read32()
182 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && in xgene_pcie_config_read32()
187 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in xgene_pcie_config_read32()
197 struct device *dev = &adev->dev; in xgene_get_csr_resource()
216 return -EINVAL; in xgene_get_csr_resource()
220 *res = *entry->res; in xgene_get_csr_resource()
227 struct device *dev = cfg->parent; in xgene_pcie_ecam_init()
230 struct resource csr; in xgene_pcie_ecam_init() local
235 return -ENOMEM; in xgene_pcie_ecam_init()
237 ret = xgene_get_csr_resource(adev, &csr); in xgene_pcie_ecam_init()
239 dev_err(dev, "can't get CSR resource\n"); in xgene_pcie_ecam_init()
242 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); in xgene_pcie_ecam_init()
243 if (IS_ERR(port->csr_base)) in xgene_pcie_ecam_init()
244 return PTR_ERR(port->csr_base); in xgene_pcie_ecam_init()
246 port->cfg_base = cfg->win; in xgene_pcie_ecam_init()
247 port->version = ipversion; in xgene_pcie_ecam_init()
249 cfg->priv = port; in xgene_pcie_ecam_init()
286 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; in xgene_pcie_set_ib_mask()
314 port->link_up = false; in xgene_pcie_linkup()
317 port->link_up = true; in xgene_pcie_linkup()
326 struct device *dev = port->dev; in xgene_pcie_init_port()
329 port->clk = clk_get(dev, NULL); in xgene_pcie_init_port()
330 if (IS_ERR(port->clk)) { in xgene_pcie_init_port()
332 return -ENODEV; in xgene_pcie_init_port()
335 rc = clk_prepare_enable(port->clk); in xgene_pcie_init_port()
347 struct device *dev = port->dev; in xgene_pcie_map_reg()
350 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); in xgene_pcie_map_reg()
351 port->csr_base = devm_pci_remap_cfg_resource(dev, res); in xgene_pcie_map_reg()
352 if (IS_ERR(port->csr_base)) in xgene_pcie_map_reg()
353 return PTR_ERR(port->csr_base); in xgene_pcie_map_reg()
356 port->cfg_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
357 if (IS_ERR(port->cfg_base)) in xgene_pcie_map_reg()
358 return PTR_ERR(port->cfg_base); in xgene_pcie_map_reg()
359 port->cfg_addr = res->start; in xgene_pcie_map_reg()
368 struct device *dev = port->dev; in xgene_pcie_setup_ob_reg()
383 mask = ~(size - 1) | flag; in xgene_pcie_setup_ob_reg()
398 u64 addr = port->cfg_addr; in xgene_pcie_setup_cfg_reg()
409 struct device *dev = port->dev; in xgene_pcie_map_ranges()
411 resource_list_for_each_entry(window, &bridge->windows) { in xgene_pcie_map_ranges()
412 struct resource *res = window->res; in xgene_pcie_map_ranges()
420 pci_pio_to_address(res->start), in xgene_pcie_map_ranges()
421 res->start - window->offset); in xgene_pcie_map_ranges()
424 if (res->flags & IORESOURCE_PREFETCH) in xgene_pcie_map_ranges()
426 res->start, in xgene_pcie_map_ranges()
427 res->start - in xgene_pcie_map_ranges()
428 window->offset); in xgene_pcie_map_ranges()
431 res->start, in xgene_pcie_map_ranges()
432 res->start - in xgene_pcie_map_ranges()
433 window->offset); in xgene_pcie_map_ranges()
439 return -EINVAL; in xgene_pcie_map_ranges()
457 * X-Gene PCIe support maximum 3 inbound memory regions
477 return -EINVAL; in xgene_pcie_select_ib_reg()
483 void __iomem *cfg_base = port->cfg_base; in xgene_pcie_setup_ib_reg()
484 struct device *dev = port->dev; in xgene_pcie_setup_ib_reg()
487 u64 cpu_addr = range->cpu_addr; in xgene_pcie_setup_ib_reg()
488 u64 pci_addr = range->pci_addr; in xgene_pcie_setup_ib_reg()
489 u64 size = range->size; in xgene_pcie_setup_ib_reg()
490 u64 mask = ~(size - 1) | EN_REG; in xgene_pcie_setup_ib_reg()
495 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); in xgene_pcie_setup_ib_reg()
497 dev_warn(dev, "invalid pcie dma-range config\n"); in xgene_pcie_setup_ib_reg()
501 if (range->flags & IORESOURCE_PREFETCH) in xgene_pcie_setup_ib_reg()
527 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); in xgene_pcie_setup_ib_reg()
532 struct device_node *np = port->node; in xgene_pcie_parse_map_dma_ranges()
535 struct device *dev = port->dev; in xgene_pcie_parse_map_dma_ranges()
539 dev_err(dev, "missing dma-ranges property\n"); in xgene_pcie_parse_map_dma_ranges()
540 return -EINVAL; in xgene_pcie_parse_map_dma_ranges()
543 /* Get the dma-ranges from DT */ in xgene_pcie_parse_map_dma_ranges()
545 u64 end = range.cpu_addr + range.size - 1; in xgene_pcie_parse_map_dma_ranges()
547 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", in xgene_pcie_parse_map_dma_ranges()
565 struct device *dev = port->dev; in xgene_pcie_setup()
584 if (!port->link_up) in xgene_pcie_setup()
587 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); in xgene_pcie_setup()
599 struct device *dev = &pdev->dev; in xgene_pcie_probe()
600 struct device_node *dn = dev->of_node; in xgene_pcie_probe()
607 return -ENOMEM; in xgene_pcie_probe()
611 port->node = of_node_get(dn); in xgene_pcie_probe()
612 port->dev = dev; in xgene_pcie_probe()
614 port->version = XGENE_PCIE_IP_VER_UNKN; in xgene_pcie_probe()
615 if (of_device_is_compatible(port->node, "apm,xgene-pcie")) in xgene_pcie_probe()
616 port->version = XGENE_PCIE_IP_VER_1; in xgene_pcie_probe()
630 bridge->sysdata = port; in xgene_pcie_probe()
631 bridge->ops = &xgene_pcie_ops; in xgene_pcie_probe()
637 {.compatible = "apm,xgene-pcie",},
643 .name = "xgene-pcie",