i2c/busses/i2c-octeon-core.h

1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <linux/clk.h>
8 #include <linux/i2c-smbus.h>
42 #define TWSI_CTL_STA		0x20	/* Controller-mode start, HW clears when done */
43 #define TWSI_CTL_STP		0x10	/* Controller-mode stop, HW clears when done */
101 #define OCTEON_REG_SW_TWSI(x)		((x)->roff.sw_twsi)
102 #define OCTEON_REG_TWSI_INT(x)		((x)->roff.twsi_int)
103 #define OCTEON_REG_SW_TWSI_EXT(x)	((x)->roff.sw_twsi_ext)
104 #define OCTEON_REG_MODE(x)		((x)->roff.mode)
118 	struct clk *clk;  member
145  * octeon_i2c_reg_write - write an I2C core register
150  * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
157 	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_write()
159 		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_write()
160 		if (--tries < 0)  in octeon_i2c_reg_write()
171  * octeon_i2c_reg_read - read lower bits of an I2C core register
177  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
185 	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_read()
187 		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_read()
188 		if (--tries < 0) {  in octeon_i2c_reg_read()
191 				*error = -EIO;  in octeon_i2c_reg_read()
207  * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
214 	return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));  in octeon_i2c_read_int()
218  * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
224 	octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));  in octeon_i2c_write_int()
231  * octeon_i2c_is_otx2 - check for chip ID
238 	u32 chip_id = FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device);  in octeon_i2c_is_otx2()