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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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/linux-6.12.1/drivers/pci/pcie/
Daspm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
44 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); in pci_save_ltr_state()
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
78 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n", in pci_configure_aspm_l1ss()
85 u16 l1ss = pdev->l1ss; in pci_save_aspm_l1ss_state()
89 * Save L1 substate configuration. The ASPM L0s/L1 configuration in pci_save_aspm_l1ss_state()
99 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
317 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dnbio_v2_3.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
70 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); in nbio_v2_3_remap_hdp_registers()
72 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); in nbio_v2_3_remap_hdp_registers()
177 lower_32_bits(adev->doorbell.base)); in nbio_v2_3_enable_doorbell_selfring_aperture()
179 upper_32_bits(adev->doorbell.base)); in nbio_v2_3_enable_doorbell_selfring_aperture()
212 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v2_3_ih_control()
216 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi in nbio_v2_3_ih_control()
217 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN in nbio_v2_3_ih_control()
222 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ in nbio_v2_3_ih_control()
234 if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) in nbio_v2_3_update_medium_grain_clock_gating()
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/linux-6.12.1/include/uapi/linux/
Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
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/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dar9002_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
[all …]
Dar9003_hw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], in ar9003_hw_init_mode_regs()
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], in ar9003_hw_init_mode_regs()
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], in ar9003_hw_init_mode_regs()
63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], in ar9003_hw_init_mode_regs()
67 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9003_hw_init_mode_regs()
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
37 #include "pcie-rockchip.h"
76 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
87 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
88 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
93 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
105 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
132 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
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Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
196 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
197 #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
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/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
[all …]
Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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/linux-6.12.1/drivers/net/wireless/ath/ath12k/
Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
33 /* BAR0 + 4k is always accessible, and no
35 * 4K - 32 = 0xFE0
80 "mhi-er0",
81 "mhi-er1",
98 "host2wbm-desc-feed",
99 "host2reo-re-injection",
100 "host2reo-command",
[all …]
/linux-6.12.1/arch/sh/drivers/pci/
Dpcie-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Express Support for the SH7786
5 * Copyright (C) 2009 - 2011 Paul Mundt
15 #include <linux/dma-map-ops.h>
21 #include "pcie-sh7786.h"
46 .end = 0xfd000000 + SZ_8M - 1,
51 .end = 0xc0000000 + SZ_512M - 1,
56 .end = 0x10000000 + SZ_64M - 1,
61 .end = 0xfe100000 + SZ_1M - 1,
70 .end = 0xfd800000 + SZ_8M - 1,
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/linux-6.12.1/drivers/net/wireless/intel/iwlegacy/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 #include <linux/dma-mapping.h>
39 return -ETIMEDOUT; in _il_poll_bit()
48 spin_lock_irqsave(&p->reg_lock, reg_flags); in il_set_bit()
50 spin_unlock_irqrestore(&p->reg_lock, reg_flags); in il_set_bit()
59 spin_lock_irqsave(&p->reg_lock, reg_flags); in il_clear_bit()
61 spin_unlock_irqrestore(&p->reg_lock, reg_flags); in il_clear_bit()
79 * to/from host DRAM when sleeping/waking for power-saving. in _il_grab_nic_access()
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/linux-6.12.1/drivers/net/ethernet/atheros/atl1c/
Datl1c_main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
14 * atl1c_pci_tbl - PCI Device ID Table
98 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_pcie_patch()
107 /* aspm/PCIE setting only for l2cb 1.0 */ in atl1c_pcie_patch()
108 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) { in atl1c_pcie_patch()
121 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) { in atl1c_pcie_patch()
131 /* FIXME: no need any more ? */
133 * atl1c_init_pcie - init PCIE module
[all …]
/linux-6.12.1/drivers/net/ethernet/atheros/alx/
Dhw.c28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
58 return -ETIMEDOUT; in alx_wait_mdio_idle()
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
[all …]
/linux-6.12.1/drivers/pci/
Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
91 int ret = -ENOTTY; in pcie_failed_link_retrain()
94 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
103 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
170 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
171 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
172 (f->vendor == dev->vendor || in pci_do_fixups()
[all …]
/linux-6.12.1/drivers/net/ethernet/realtek/
Dr8169_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
26 #include <linux/dma-mapping.h>
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/e1000e/
Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
136 writel(val, hw->hw_addr + reg); in __ew32()
140 * e1000_regdump - register printout routine
150 switch (reginfo->ofs) { in e1000_regdump()
164 pr_info("%-15s %08x\n", in e1000_regdump()
[all …]
/linux-6.12.1/include/linux/
Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
60 * The PCI interface treats multi-function devices as independent
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
86 return kobject_name(&slot->kobj); in pci_slot_name()
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
[all …]

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