Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
45 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2); in ar9002_hw_init_mode_regs()
46 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2); in ar9002_hw_init_mode_regs()
48 INIT_INI_ARRAY(&ah->iniModesFastClock, in ar9002_hw_init_mode_regs()
51 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160); in ar9002_hw_init_mode_regs()
52 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160); in ar9002_hw_init_mode_regs()
54 INIT_INI_ARRAY(&ah->iniAddac, in ar9002_hw_init_mode_regs()
57 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160); in ar9002_hw_init_mode_regs()
60 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100); in ar9002_hw_init_mode_regs()
61 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100); in ar9002_hw_init_mode_regs()
62 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100); in ar9002_hw_init_mode_regs()
64 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes); in ar9002_hw_init_mode_regs()
65 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common); in ar9002_hw_init_mode_regs()
66 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac); in ar9002_hw_init_mode_regs()
71 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain); in ar9002_hw_init_mode_regs()
75 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100); in ar9002_hw_init_mode_regs()
77 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC); in ar9002_hw_init_mode_regs()
82 struct ar5416IniArray *addac = &ah->iniAddac; in ar9002_hw_init_mode_regs()
83 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns; in ar9002_hw_init_mode_regs()
86 data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar9002_hw_init_mode_regs()
88 return -ENOMEM; in ar9002_hw_init_mode_regs()
90 memcpy(data, addac->ia_array, size); in ar9002_hw_init_mode_regs()
91 addac->ia_array = data; in ar9002_hw_init_mode_regs()
99 INIT_INI_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_init_mode_regs()
101 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_init_mode_regs()
111 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_17) { in ar9280_20_hw_init_rxgain_ini()
112 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); in ar9280_20_hw_init_rxgain_ini()
115 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
118 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
121 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
124 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
131 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19) { in ar9280_20_hw_init_txgain_ini()
133 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
136 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
139 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
147 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
150 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
156 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); in ar9002_hw_init_mode_gain_regs()
159 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9002_hw_init_mode_gain_regs()
167 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
175 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
178 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
183 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
186 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
194 * Helper for ASPM support.
196 * Disable PLL when in L0s as well as receiver clock when in L1.
216 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { in ar9002_hw_configpcipowersave()
217 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
218 INI_RA(&ah->iniPcieSerdes, i, 1)); in ar9002_hw_configpcipowersave()
232 * Ignore ah->ah_config.pcie_clock_req setting for in ar9002_hw_configpcipowersave()
233 * pre-AR9280 11n in ar9002_hw_configpcipowersave()
262 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
263 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) in ar9002_hw_configpcipowersave()
291 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
292 val = ah->config.pcie_waen; in ar9002_hw_configpcipowersave()
310 /* WAR for ASPM system hang */ in ar9002_hw_configpcipowersave()
363 return -EOPNOTSUPP; in ar9002_hw_rf_claim()
366 ah->hw_version.analog5GhzRev = val; in ar9002_hw_rf_claim()
387 ah->config.hw_hang_checks |= HW_BB_RIFS_HANG; in ar9002_hw_init_hang_checks()
388 ah->config.hw_hang_checks |= HW_BB_DFS_HANG; in ar9002_hw_init_hang_checks()
392 ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG; in ar9002_hw_init_hang_checks()
395 ah->config.hw_hang_checks |= HW_MAC_HANG; in ar9002_hw_init_hang_checks()
409 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; in ar9002_hw_attach_ops()
410 priv_ops->init_hang_checks = ar9002_hw_init_hang_checks; in ar9002_hw_attach_ops()
412 ops->config_pci_powersave = ar9002_hw_configpcipowersave; in ar9002_hw_attach_ops()
438 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { in ar9002_hw_load_ani_reg()
439 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); in ar9002_hw_load_ani_reg()
440 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); in ar9002_hw_load_ani_reg()