Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
160 /* 0x3c-0x3d are same as for htype 0 */
191 /* 0x3c-0x3d are same as for htype 0 */
199 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
205 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
206 /* 0x48-0x7f reserved */
217 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
219 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
222 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
224 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
227 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
256 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
272 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
274 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
283 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
295 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
311 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
312 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
316 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */
317 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */
318 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */
319 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */
320 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */
321 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */
323 /* MSI-X registers (in MSI-X capability) */
327 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
337 /* MSI-X Table entry format (in memory mapped by a BAR) */
353 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
354 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
382 /* 0-5 map to BARs 0-5 respectively */
388 /* 9-14 map to VF BARs 0-5 respectively */
391 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
394 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
398 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
399 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
402 /* 0x08-0xfc reserved */
411 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
414 /* PCI-X registers (Type 0 (non-bridge) devices) */
435 #define PCI_X_STATUS 4 /* PCI-X capabilities */
438 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
454 /* PCI-X registers (Type 1 (bridge) devices) */
460 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
482 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
483 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
492 #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */
497 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
503 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
517 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
528 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
543 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
544 #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
545 #define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */
546 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
554 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
555 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
592 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
593 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
597 #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */
605 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
621 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
634 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
656 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
664 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
665 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
669 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
703 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
707 /* Extended Capabilities (PCI-X 2.0 and Express) */
719 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
722 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
723 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
742 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
782 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
796 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
804 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
861 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
862 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
901 /* Alternative Routing-ID Interpretation */
948 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
951 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
957 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
984 #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
1001 #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
1006 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
1023 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1029 #define PCI_TPH_LOC_NONE 0x000 /* no location */
1031 #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
1034 #define PCI_TPH_BASE_SIZEOF 0xc /* size with no ST table */
1085 /* ASPM L1 PM Substates */
1087 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1088 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1089 #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */
1090 #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */
1096 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1097 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1098 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */
1099 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */
1109 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1110 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
1114 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1178 /* DOE Data Object - note not actually registers */