Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
44 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); in pci_save_ltr_state()
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
78 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n", in pci_configure_aspm_l1ss()
85 u16 l1ss = pdev->l1ss; in pci_save_aspm_l1ss_state()
89 * Save L1 substate configuration. The ASPM L0s/L1 configuration in pci_save_aspm_l1ss_state()
99 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
107 struct pci_dev *parent = pdev->bus->self; in pci_restore_aspm_l1ss_state()
120 if (!pdev->l1ss || !parent->l1ss) in pci_restore_aspm_l1ss_state()
128 cap = &cl_save_state->cap.data[0]; in pci_restore_aspm_l1ss_state()
131 cap = &pl_save_state->cap.data[0]; in pci_restore_aspm_l1ss_state()
135 /* Make sure L0s/L1 are disabled before updating L1SS config */ in pci_restore_aspm_l1ss_state()
150 pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
152 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
166 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2); in pci_restore_aspm_l1ss_state()
167 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2); in pci_restore_aspm_l1ss_state()
168 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1); in pci_restore_aspm_l1ss_state()
169 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1); in pci_restore_aspm_l1ss_state()
173 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
175 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
179 /* Restore L0s/L1 if they were enabled */ in pci_restore_aspm_l1ss_state()
195 #define PCIE_LINK_STATE_L0S_UP BIT(0) /* Upstream direction L0s state */
196 #define PCIE_LINK_STATE_L0S_DW BIT(1) /* Downstream direction L0s state */
214 /* ASPM state */
215 u32 aspm_support:7; /* Supported ASPM state */
216 u32 aspm_enabled:7; /* Enabled ASPM state */
217 u32 aspm_capable:7; /* Capable ASPM state with latency */
218 u32 aspm_default:7; /* Default ASPM state by BIOS */
219 u32 aspm_disable:7; /* Disabled ASPM state */
263 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
264 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
273 /* Disable ASPM and Clock PM */ in policy_to_aspm_state()
276 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
282 return link->aspm_default; in policy_to_aspm_state()
291 /* Disable ASPM and Clock PM */ in policy_to_clkpm_state()
298 return link->clkpm_default; in policy_to_clkpm_state()
315 * Update ASPM and CLKREQ bits of LNKCTL in save_state. We only in pci_update_aspm_saved_state()
323 cap = (u16 *)&save_state->cap.data[0]; in pci_update_aspm_saved_state()
330 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
333 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_set_clkpm_nocheck()
339 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
348 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
351 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
362 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
365 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
376 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
377 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
378 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
379 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
385 * common clock. That will reduce the ASPM state exit latency.
391 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock()
392 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
397 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
416 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
426 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n"); in pcie_aspm_configure_common_clock()
431 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
433 child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC; in pcie_aspm_configure_common_clock()
442 if (pcie_retrain_link(link->pdev, true)) { in pcie_aspm_configure_common_clock()
445 pci_err(parent, "ASPM: Could not configure common clock\n"); in pcie_aspm_configure_common_clock()
446 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
449 child_old_ccc[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
455 /* Convert L0s latency encoding to ns */
465 /* Convert L0s acceptable latency encoding to ns */
519 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max in encode_l12_threshold()
555 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
556 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
559 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
561 /* Calculate endpoint L0s acceptable latency */ in pcie_aspm_check_latency()
562 encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap); in pcie_aspm_check_latency()
566 encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap); in pcie_aspm_check_latency()
570 struct pci_dev *dev = pci_function_0(link->pdev->subordinate); in pcie_aspm_check_latency()
573 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, in pcie_aspm_check_latency()
582 /* Check upstream direction L0s latency */ in pcie_aspm_check_latency()
583 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_UP) && in pcie_aspm_check_latency()
585 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_UP; in pcie_aspm_check_latency()
587 /* Check downstream direction L0s latency */ in pcie_aspm_check_latency()
588 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_DW) && in pcie_aspm_check_latency()
590 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_DW; in pcie_aspm_check_latency()
594 * more microsecond for L1. Spec doesn't mention L0s. in pcie_aspm_check_latency()
605 if ((link->aspm_capable & PCIE_LINK_STATE_L1) && in pcie_aspm_check_latency()
607 link->aspm_capable &= ~PCIE_LINK_STATE_L1; in pcie_aspm_check_latency()
610 link = link->parent; in pcie_aspm_check_latency()
618 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info()
653 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l12_info()
654 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l12_info()
664 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); in aspm_calc_l12_info()
665 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); in aspm_calc_l12_info()
666 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); in aspm_calc_l12_info()
667 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2); in aspm_calc_l12_info()
679 child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
682 parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
687 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
688 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
691 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
695 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
699 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
706 parent->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
709 child->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
716 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_l1ss_init()
720 if (!parent->l1ss || !child->l1ss) in aspm_l1ss_init()
724 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
726 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
736 * to this device, we can't use ASPM L1.2 because it relies on the in aspm_l1ss_init()
739 if (!child->ltr_path) in aspm_l1ss_init()
743 link->aspm_support |= PCIE_LINK_STATE_L1_1; in aspm_l1ss_init()
745 link->aspm_support |= PCIE_LINK_STATE_L1_2; in aspm_l1ss_init()
747 link->aspm_support |= PCIE_LINK_STATE_L1_1_PCIPM; in aspm_l1ss_init()
749 link->aspm_support |= PCIE_LINK_STATE_L1_2_PCIPM; in aspm_l1ss_init()
752 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
755 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
759 link->aspm_enabled |= PCIE_LINK_STATE_L1_1; in aspm_l1ss_init()
761 link->aspm_enabled |= PCIE_LINK_STATE_L1_2; in aspm_l1ss_init()
763 link->aspm_enabled |= PCIE_LINK_STATE_L1_1_PCIPM; in aspm_l1ss_init()
765 link->aspm_enabled |= PCIE_LINK_STATE_L1_2_PCIPM; in aspm_l1ss_init()
767 if (link->aspm_support & PCIE_LINK_STATE_L1_2_MASK) in aspm_l1ss_init()
773 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init()
776 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
779 /* Set enabled/disable so that we will disable ASPM later */ in pcie_aspm_cap_init()
780 link->aspm_enabled = PCIE_LINK_STATE_ASPM_ALL; in pcie_aspm_cap_init()
781 link->aspm_disable = PCIE_LINK_STATE_ASPM_ALL; in pcie_aspm_cap_init()
786 * If ASPM not supported, don't mess with the clocks and link, in pcie_aspm_cap_init()
798 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
799 * clock configuration. L0s & L1 exit latencies in the otherwise in pcie_aspm_cap_init()
800 * read-only Link Capabilities may change depending on common clock in pcie_aspm_cap_init()
809 * Setup L0s state in pcie_aspm_cap_init()
811 * Note that we must not enable L0s in either direction on a in pcie_aspm_cap_init()
813 * support L0s. in pcie_aspm_cap_init()
816 link->aspm_support |= PCIE_LINK_STATE_L0S; in pcie_aspm_cap_init()
819 link->aspm_enabled |= PCIE_LINK_STATE_L0S_UP; in pcie_aspm_cap_init()
821 link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW; in pcie_aspm_cap_init()
825 link->aspm_support |= PCIE_LINK_STATE_L1; in pcie_aspm_cap_init()
828 link->aspm_enabled |= PCIE_LINK_STATE_L1; in pcie_aspm_cap_init()
833 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
836 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
839 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
848 /* Configure the ASPM L1 substates */
852 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss()
854 enable_req = (link->aspm_enabled ^ state) & state; in pcie_config_aspm_l1ss()
858 * - When enabling L1.x, enable bit at parent first, then at child in pcie_config_aspm_l1ss()
859 * - When disabling L1.x, disable bit at child first, then at parent in pcie_config_aspm_l1ss()
860 * - When enabling ASPM L1.x, need to disable L1 in pcie_config_aspm_l1ss()
862 * - The ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
870 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
872 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
896 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
898 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
911 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link()
912 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
915 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
922 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
924 state |= (link->aspm_enabled & PCIE_LINK_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
928 if (link->aspm_enabled == state) in pcie_config_aspm_link()
930 /* Convert ASPM state to upstream/downstream ASPM register state */ in pcie_config_aspm_link()
940 if (link->aspm_capable & PCIE_LINK_STATE_L1SS) in pcie_config_aspm_link()
945 * same setting for ASPM. Enabling ASPM L1 should be done in in pcie_config_aspm_link()
947 * versa for disabling ASPM L1. Spec doesn't mention L0S. in pcie_config_aspm_link()
951 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
956 link->aspm_enabled = state; in pcie_config_aspm_link()
958 /* Update latest ASPM configuration in saved context */ in pcie_config_aspm_link()
959 pci_save_aspm_l1ss_state(link->downstream); in pcie_config_aspm_link()
960 pci_update_aspm_saved_state(link->downstream); in pcie_config_aspm_link()
969 link = link->parent; in pcie_config_aspm_path()
975 link->pdev->link_state = NULL; in free_link_state()
986 * very strange. Disable ASPM for the whole slot in pcie_aspm_sanity_check()
988 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
990 return -EINVAL; in pcie_aspm_sanity_check()
993 * If ASPM is disabled then we're not going to change in pcie_aspm_sanity_check()
995 * pre-1.1 device in pcie_aspm_sanity_check()
1002 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
1007 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
1008 return -EINVAL; in pcie_aspm_sanity_check()
1022 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
1023 link->pdev = pdev; in alloc_pcie_link_state()
1024 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
1027 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
1035 !pdev->bus->parent->self) { in alloc_pcie_link_state()
1036 link->root = link; in alloc_pcie_link_state()
1040 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
1046 link->parent = parent; in alloc_pcie_link_state()
1047 link->root = link->parent->root; in alloc_pcie_link_state()
1050 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
1051 pdev->link_state = link; in alloc_pcie_link_state()
1059 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) in pcie_aspm_update_sysfs_visibility()
1060 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group); in pcie_aspm_update_sysfs_visibility()
1076 if (pdev->link_state) in pcie_aspm_init_link_state()
1089 pdev->bus->self) in pcie_aspm_init_link_state()
1093 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
1101 * Setup initial ASPM state. Note that we need to configure in pcie_aspm_init_link_state()
1112 * link policy setting. Enabling ASPM on broken hardware can cripple in pcie_aspm_init_link_state()
1113 * it even before the driver has had a chance to disable ASPM, so in pcie_aspm_init_link_state()
1114 * default to a safe level right now. If we're enabling ASPM beyond in pcie_aspm_init_link_state()
1138 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1141 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1150 struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); in pci_configure_ltr()
1164 pdev->ltr_path = 1; in pci_configure_ltr()
1169 if (bridge && bridge->ltr_path) in pci_configure_ltr()
1170 pdev->ltr_path = 1; in pci_configure_ltr()
1175 if (!host->native_ltr) in pci_configure_ltr()
1186 pdev->ltr_path = 1; in pci_configure_ltr()
1191 * If we're configuring a hot-added device, LTR was likely in pci_configure_ltr()
1192 * disabled in the upstream bridge, so re-enable it before enabling in pci_configure_ltr()
1196 if (bridge && bridge->ltr_path) { in pci_configure_ltr()
1200 pdev->ltr_path = 1; in pci_configure_ltr()
1208 BUG_ON(root->parent); in pcie_update_aspm_capable()
1210 if (link->root != root) in pcie_update_aspm_capable()
1212 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
1216 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
1217 if (link->root != root) in pcie_update_aspm_capable()
1219 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
1231 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state()
1234 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
1240 link = parent->link_state; in pcie_aspm_exit_link_state()
1241 root = link->root; in pcie_aspm_exit_link_state()
1242 parent_link = link->parent; in pcie_aspm_exit_link_state()
1245 * link->downstream is a pointer to the pci_dev of function 0. If in pcie_aspm_exit_link_state()
1247 * so we can't use link->downstream again. Free the link state to in pcie_aspm_exit_link_state()
1250 * If we're removing a non-0 function, it's possible we could in pcie_aspm_exit_link_state()
1252 * programming the same ASPM Control value for all functions of in pcie_aspm_exit_link_state()
1253 * multi-function devices, so disable ASPM for all of them. in pcie_aspm_exit_link_state()
1256 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1275 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_pm_state_change()
1286 pcie_update_aspm_capable(link->root); in pcie_aspm_pm_state_change()
1295 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1323 return bridge->link_state; in pcie_aspm_get_link()
1353 return -EINVAL; in __pci_disable_link_state()
1355 * A driver requested that ASPM be disabled on this device, but in __pci_disable_link_state()
1356 * if we don't have permission to manage ASPM (e.g., on ACPI in __pci_disable_link_state()
1363 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n"); in __pci_disable_link_state()
1364 return -EPERM; in __pci_disable_link_state()
1370 link->aspm_disable |= pci_calc_aspm_disable_mask(state); in __pci_disable_link_state()
1374 link->clkpm_disable = 1; in __pci_disable_link_state()
1392 * pci_disable_link_state - Disable device's link state, so the link will
1393 * never enter specific states. Note that if the BIOS didn't grant ASPM
1398 * @state: ASPM link state to disable
1411 return -EINVAL; in __pci_enable_link_state()
1413 * A driver requested that ASPM be enabled on this device, but in __pci_enable_link_state()
1414 * if we don't have permission to manage ASPM (e.g., on ACPI in __pci_enable_link_state()
1419 pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n"); in __pci_enable_link_state()
1420 return -EPERM; in __pci_enable_link_state()
1426 link->aspm_default = pci_calc_aspm_enable_mask(state); in __pci_enable_link_state()
1429 link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0; in __pci_enable_link_state()
1439 * pci_enable_link_state - Clear and set the default device link state so that
1441 * BIOS didn't grant ASPM control to the OS, this does nothing because we can't
1446 * @state: Mask of ASPM link states to enable
1455 * pci_enable_link_state_locked - Clear and set the default device link state
1457 * the BIOS didn't grant ASPM control to the OS, this does nothing because we
1462 * @state: Mask of ASPM link states to enable
1481 return -EPERM; in pcie_aspm_set_policy()
1516 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1531 return link->aspm_enabled; in pcie_aspm_enabled()
1542 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0); in aspm_attr_show_common()
1554 return -EINVAL; in aspm_attr_store_common()
1560 link->aspm_disable &= ~state; in aspm_attr_store_common()
1563 link->aspm_disable &= ~PCIE_LINK_STATE_L1; in aspm_attr_store_common()
1565 link->aspm_disable |= state; in aspm_attr_store_common()
1567 link->aspm_disable |= PCIE_LINK_STATE_L1SS; in aspm_attr_store_common()
1588 ASPM_ATTR(l0s_aspm, L0S) in ASPM_ATTR() argument
1601 return sysfs_emit(buf, "%d\n", link->clkpm_enabled); in ASPM_ATTR()
1613 return -EINVAL; in clkpm_store()
1618 link->clkpm_disable = !state_enable; in clkpm_store()
1665 return link->clkpm_capable ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1667 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1682 pr_info("PCIe ASPM is disabled\n"); in pcie_aspm_disable()
1685 pr_info("PCIe ASPM is forcibly enabled\n"); in pcie_aspm_disable()
1695 * Disabling ASPM is intended to prevent the kernel from modifying in pcie_no_aspm()