Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
317 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
322 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_icc_set()
333 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
335 * transitioning to Gen-2 speed in apply_bad_link_workaround()
337 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
340 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
341 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
342 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
346 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
349 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
352 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
361 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
362 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
370 if (!pcie->of_data->has_sbr_reset_fix && in tegra_pcie_rp_irq_handler()
396 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
399 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
406 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
408 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
417 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
421 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
425 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
430 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
465 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_irq_thread()
466 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
469 if (test_and_clear_bit(0, &pcie->link_status)) in tegra_pcie_ep_irq_thread()
474 if (pcie->of_data->has_ltr_req_fix) in tegra_pcie_ep_irq_thread()
478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
487 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
511 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
534 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
535 set_bit(0, &pcie->link_status); in tegra_pcie_ep_hard_irq()
554 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
565 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_rd_own_conf()
572 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
575 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_rd_own_conf()
587 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_wr_own_conf()
594 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
597 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_wr_own_conf()
615 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
617 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
624 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
626 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
633 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
639 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
641 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
650 dev_get_drvdata(s->private); in aspm_state_cnt()
653 seq_printf(s, "Tx L0s entry count : %u\n", in aspm_state_cnt()
656 seq_printf(s, "Rx L0s entry count : %u\n", in aspm_state_cnt()
669 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
673 /* Re-enable counting */ in aspm_state_cnt()
676 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
684 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
688 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
690 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci, in init_host_aspm()
693 /* Enable ASPM counters */ in init_host_aspm()
696 dw_pcie_writel_dbi(pci, pcie->ras_des_cap + in init_host_aspm()
700 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
702 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
703 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
704 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
706 /* Program L0s and L1 entrance latencies */ in init_host_aspm()
709 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
716 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
737 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_enable_system_interrupts()
743 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
745 val |= pcie->of_data->cdm_chk_int_en_bit; in tegra_pcie_enable_system_interrupts()
754 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
756 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); in tegra_pcie_enable_system_interrupts()
758 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
761 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
829 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
833 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
872 pcie->of_data->gen4_preset_vec); in config_gen3_gen4_eq_presets()
888 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
890 if (!pcie->pcie_cap_base) in tegra_pcie_dw_host_init()
891 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_dw_host_init()
913 if (pcie->enable_srns) { in tegra_pcie_dw_host_init()
914 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_dw_host_init()
917 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in tegra_pcie_dw_host_init()
925 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
926 if (!pcie->supports_clkreq) { in tegra_pcie_dw_host_init()
931 if (!pcie->of_data->has_l1ss_exit_fix) { in tegra_pcie_dw_host_init()
937 if (pcie->update_fc_fixup) { in tegra_pcie_dw_host_init()
943 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_dw_host_init()
951 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_dw_start_link()
955 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_start_link()
956 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
973 /* De-assert RST */ in tegra_pcie_dw_start_link()
1001 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_start_link()
1002 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_start_link()
1008 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_start_link()
1009 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_start_link()
1033 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1042 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1057 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1059 while (phy_count--) { in tegra_pcie_disable_phy()
1060 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1061 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1070 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1071 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1075 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1083 while (i--) { in tegra_pcie_enable_phy()
1084 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1086 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1094 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_dw_parse_dt()
1095 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1098 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in tegra_pcie_dw_parse_dt()
1099 if (!pcie->dbi_res) { in tegra_pcie_dw_parse_dt()
1100 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); in tegra_pcie_dw_parse_dt()
1101 return -ENODEV; in tegra_pcie_dw_parse_dt()
1104 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1106 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1110 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1111 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1113 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1116 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1117 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1119 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1120 "Failed to read ASPM L0s Entrance latency: %d\n", ret); in tegra_pcie_dw_parse_dt()
1122 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1124 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1128 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1130 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1134 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1136 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1140 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1142 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1143 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1146 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) { in tegra_pcie_dw_parse_dt()
1147 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) in tegra_pcie_dw_parse_dt()
1148 pcie->enable_ext_refclk = true; in tegra_pcie_dw_parse_dt()
1150 pcie->enable_ext_refclk = in tegra_pcie_dw_parse_dt()
1151 of_property_read_bool(pcie->dev->of_node, in tegra_pcie_dw_parse_dt()
1152 "nvidia,enable-ext-refclk"); in tegra_pcie_dw_parse_dt()
1155 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1156 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1158 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1159 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1161 if (pcie->of_data->version == TEGRA234_DWC_IP_VER) in tegra_pcie_dw_parse_dt()
1162 pcie->enable_srns = in tegra_pcie_dw_parse_dt()
1163 of_property_read_bool(np, "nvidia,enable-srns"); in tegra_pcie_dw_parse_dt()
1165 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1169 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1170 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1171 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1174 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1177 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1183 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1184 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1186 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1187 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1190 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1193 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1196 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1210 * Controller-5 doesn't need to have its state set by BPMP-FW in in tegra_pcie_bpmp_set_ctrl_state()
1213 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1220 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1230 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1245 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1248 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1258 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1263 struct dw_pcie_rp *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1272 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1276 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1278 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1285 dev_err(pcie->dev, "Failed to find downstream devices\n"); in tegra_pcie_downstream_dev_to_D0()
1289 list_for_each_entry(pdev, &root_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1290 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1292 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1294 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1301 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1302 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1303 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1304 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1306 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1309 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1310 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1311 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1312 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1314 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1324 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1325 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1327 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1333 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1334 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1336 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1344 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1347 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1353 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1354 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1360 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1361 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1362 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1363 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1374 dev_err(pcie->dev, in tegra_pcie_config_controller()
1375 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1379 if (pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1382 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret); in tegra_pcie_config_controller()
1391 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1393 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1397 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1399 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1403 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1405 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1410 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_config_controller()
1423 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1428 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1443 if (pcie->enable_srns || pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1456 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1465 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1468 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1473 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1475 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1477 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1481 if (pcie->enable_ext_refclk) in tegra_pcie_config_controller()
1493 ret = reset_control_assert(pcie->core_rst); in tegra_pcie_unconfig_controller()
1495 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1499 ret = reset_control_assert(pcie->core_apb_rst); in tegra_pcie_unconfig_controller()
1501 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1503 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_unconfig_controller()
1505 ret = regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_unconfig_controller()
1507 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in tegra_pcie_unconfig_controller()
1511 if (pcie->enable_ext_refclk) { in tegra_pcie_unconfig_controller()
1514 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret); in tegra_pcie_unconfig_controller()
1519 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in tegra_pcie_unconfig_controller()
1520 pcie->cid, ret); in tegra_pcie_unconfig_controller()
1525 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1526 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_init_controller()
1533 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1537 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1552 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1559 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1569 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1570 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1585 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1597 * Some cards do not go to detect state even after de-asserting in tegra_pcie_dw_pme_turnoff()
1598 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1600 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1602 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1604 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1612 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1615 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1629 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1636 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1661 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1662 if (!pcie->link_state) { in tegra_pcie_config_rp()
1663 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1667 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in tegra_pcie_config_rp()
1669 ret = -ENOMEM; in tegra_pcie_config_rp()
1673 pcie->debugfs = debugfs_create_dir(name, NULL); in tegra_pcie_config_rp()
1691 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1699 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1705 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1707 pci_epc_deinit_notify(pcie->pci.ep.epc); in pex_ep_event_pex_rst_assert()
1708 dw_pcie_ep_cleanup(&pcie->pci.ep); in pex_ep_event_pex_rst_assert()
1710 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1714 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1716 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1718 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1720 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_assert()
1723 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", in pex_ep_event_pex_rst_assert()
1729 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); in pex_ep_event_pex_rst_assert()
1731 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1732 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1737 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1738 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1739 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1744 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1756 dev_err(pcie->dev, "Failed to enable controller %u: %d\n", in pex_ep_event_pex_rst_deassert()
1757 pcie->cid, ret); in pex_ep_event_pex_rst_deassert()
1761 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_deassert()
1770 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1776 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1828 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1831 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1846 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1848 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1858 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1859 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1864 if (!pcie->of_data->has_l1ss_exit_fix) { in pex_ep_event_pex_rst_deassert()
1870 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1874 if (pcie->enable_srns) { in pex_ep_event_pex_rst_deassert()
1875 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in pex_ep_event_pex_rst_deassert()
1878 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in pex_ep_event_pex_rst_deassert()
1882 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1884 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1887 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1896 pci_epc_init_notify(ep->epc); in pex_ep_event_pex_rst_deassert()
1899 if (pcie->of_data->has_ltr_req_fix) { in pex_ep_event_pex_rst_deassert()
1910 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1916 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1919 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1921 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1934 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1946 return -EINVAL; in tegra_pcie_ep_raise_intx_irq()
1957 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1966 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1968 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
1990 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
1991 return -EPERM; in tegra_pcie_ep_raise_irq()
2025 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
2026 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
2031 ep = &pci->ep; in tegra_pcie_config_ep()
2032 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
2034 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
2036 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
2043 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
2048 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
2051 pcie->cid); in tegra_pcie_config_ep()
2054 return -ENOMEM; in tegra_pcie_config_ep()
2057 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
2059 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
2061 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
2087 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
2101 return -ENOMEM; in tegra_pcie_dw_probe()
2103 pci = &pcie->pci; in tegra_pcie_dw_probe()
2104 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
2105 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
2106 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
2107 pcie->of_data = (struct tegra_pcie_dw_of_data *)data; in tegra_pcie_dw_probe()
2108 pci->n_fts[0] = pcie->of_data->n_fts[0]; in tegra_pcie_dw_probe()
2109 pci->n_fts[1] = pcie->of_data->n_fts[1]; in tegra_pcie_dw_probe()
2110 pp = &pci->pp; in tegra_pcie_dw_probe()
2111 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_dw_probe()
2117 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2130 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2139 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2140 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2142 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2143 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2144 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2145 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2147 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2151 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2152 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2154 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2155 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2158 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2160 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2162 return -ENODEV; in tegra_pcie_dw_probe()
2165 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2166 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2167 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2169 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2170 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2172 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2173 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2176 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2178 return -ENOMEM; in tegra_pcie_dw_probe()
2180 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2181 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2184 return -ENOMEM; in tegra_pcie_dw_probe()
2190 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2196 pcie->phys = phys; in tegra_pcie_dw_probe()
2202 return -ENODEV; in tegra_pcie_dw_probe()
2204 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2206 pci->atu_size = resource_size(atu_dma_res); in tegra_pcie_dw_probe()
2207 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2208 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2209 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2211 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2212 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2214 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2215 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2218 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2219 if (pp->irq < 0) in tegra_pcie_dw_probe()
2220 return pp->irq; in tegra_pcie_dw_probe()
2222 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2223 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2224 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2228 pcie->icc_path = devm_of_icc_get(&pdev->dev, "write"); in tegra_pcie_dw_probe()
2229 ret = PTR_ERR_OR_ZERO(pcie->icc_path); in tegra_pcie_dw_probe()
2231 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2232 dev_err_probe(&pdev->dev, ret, "failed to get write interconnect\n"); in tegra_pcie_dw_probe()
2236 switch (pcie->of_data->mode) { in tegra_pcie_dw_probe()
2238 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2239 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2241 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2247 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2254 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2258 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2260 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2274 pcie->of_data->mode); in tegra_pcie_dw_probe()
2275 ret = -EINVAL; in tegra_pcie_dw_probe()
2279 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2287 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_remove()
2288 if (!pcie->link_state) in tegra_pcie_dw_remove()
2291 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2293 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2295 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_remove()
2299 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2300 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2301 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2302 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2310 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_suspend_late()
2312 return -EPERM; in tegra_pcie_dw_suspend_late()
2315 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2319 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_suspend_late()
2334 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2349 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2356 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2362 dw_pcie_setup_rc(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2364 ret = tegra_pcie_dw_start_link(&pcie->pci); in tegra_pcie_dw_resume_noirq()
2380 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_resume_early()
2382 return -ENOTSUPP; in tegra_pcie_dw_resume_early()
2385 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2389 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_resume_early()
2406 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_shutdown()
2407 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2410 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2413 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2415 disable_irq(pcie->pci.pp.msi_irq[0]); in tegra_pcie_dw_shutdown()
2419 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_shutdown()
2421 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_shutdown()
2430 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2439 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2451 /* Gen4 - 6, 8 and 9 presets enabled */
2462 /* Gen4 - 6, 8 and 9 presets enabled */
2469 .compatible = "nvidia,tegra194-pcie",
2473 .compatible = "nvidia,tegra194-pcie-ep",
2477 .compatible = "nvidia,tegra234-pcie",
2481 .compatible = "nvidia,tegra234-pcie-ep",
2499 .name = "tegra194-pcie",