Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
58 return -ETIMEDOUT; in alx_wait_mdio_idle()
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
208 spin_lock(&hw->mdio_lock); in alx_write_phy_ext()
210 spin_unlock(&hw->mdio_lock); in alx_write_phy_ext()
219 spin_lock(&hw->mdio_lock); in alx_read_phy_dbg()
221 spin_unlock(&hw->mdio_lock); in alx_read_phy_dbg()
230 spin_lock(&hw->mdio_lock); in alx_write_phy_dbg()
232 spin_unlock(&hw->mdio_lock); in alx_write_phy_dbg()
284 /* addr should be big-endian */ in alx_read_macaddr()
301 return -EIO; in alx_get_perm_macaddr()
304 return -EIO; in alx_get_perm_macaddr()
313 return -EIO; in alx_get_perm_macaddr()
316 return -EIO; in alx_get_perm_macaddr()
321 return -EIO; in alx_get_perm_macaddr()
328 /* for example: 00-0B-6A-F6-00-DC * STAD0=6AF600DC, STAD1=000B */ in alx_set_macaddr()
345 /* 25M clk from chipset may be unstable 1s after de-assert of in alx_reset_osc()
346 * PERST, driver need re-calibrate before enter Sleep for WoL in alx_reset_osc()
350 /* restore over current protection def-val, in alx_reset_osc()
351 * this val could be reset by MAC-RST in alx_reset_osc()
354 /* a 0->1 change will update the internal val of osc */ in alx_reset_osc()
388 hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN); in alx_stop_mac()
389 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_stop_mac()
398 return -ETIMEDOUT; in alx_stop_mac()
424 /* dis l0s/l1 before mac reset */ in alx_reset_mac()
453 return -EIO; in alx_reset_mac()
458 /* restore l0s / l1 */ in alx_reset_mac()
479 /* driver control speed/duplex, hash-alg */ in alx_reset_mac()
480 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_reset_mac()
537 if (hw->lnk_patch) { in alx_reset_phy()
567 pci_read_config_word(hw->pdev, PCI_COMMAND, &val16); in alx_reset_pcie()
570 pci_write_config_word(hw->pdev, PCI_COMMAND, val16); in alx_reset_pcie()
601 /* ASPM setting */ in alx_reset_pcie()
616 mac = hw->rx_ctrl; in alx_start_mac()
617 if (hw->duplex == DUPLEX_FULL) in alx_start_mac()
622 hw->link_speed == SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 : in alx_start_mac()
625 hw->rx_ctrl = mac; in alx_start_mac()
632 hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN; in alx_cfg_mac_flowcontrol()
634 hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN; in alx_cfg_mac_flowcontrol()
637 hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN; in alx_cfg_mac_flowcontrol()
639 hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN; in alx_cfg_mac_flowcontrol()
641 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_cfg_mac_flowcontrol()
754 err = -EBUSY; in alx_setup_speed_duplex()
788 if (hw->link_speed != SPEED_UNKNOWN) { in alx_post_phy_link()
795 if ((hw->link_speed == SPEED_1000 && in alx_post_phy_link()
798 (hw->link_speed == SPEED_100 && in alx_post_phy_link()
817 if (adj_th && hw->lnk_patch) { in alx_post_phy_link()
818 if (hw->link_speed == SPEED_100) { in alx_post_phy_link()
821 } else if (hw->link_speed == SPEED_1000) { in alx_post_phy_link()
840 if (adj_th && hw->lnk_patch) { in alx_post_phy_link()
855 cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg); in alx_phy_configured()
867 struct pci_dev *pdev = hw->pdev; in alx_read_phy_link()
880 hw->link_speed = SPEED_UNKNOWN; in alx_read_phy_link()
881 hw->duplex = DUPLEX_UNKNOWN; in alx_read_phy_link()
895 hw->link_speed = SPEED_1000; in alx_read_phy_link()
898 hw->link_speed = SPEED_100; in alx_read_phy_link()
901 hw->link_speed = SPEED_10; in alx_read_phy_link()
907 hw->duplex = (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF; in alx_read_phy_link()
911 dev_err(&pdev->dev, "invalid PHY speed/duplex: 0x%x\n", giga); in alx_read_phy_link()
912 return -EINVAL; in alx_read_phy_link()
937 alx_set_macaddr(hw, hw->mac_addr); in alx_configure_basic()
946 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL); in alx_configure_basic()
954 (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT); in alx_configure_basic()
955 /* intr re-trig timeout */ in alx_configure_basic()
958 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); in alx_configure_basic()
959 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); in alx_configure_basic()
961 raw_mtu = ALX_RAW_MTU(hw->mtu); in alx_configure_basic()
964 hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE; in alx_configure_basic()
972 max_payload = pcie_get_readrq(hw->pdev) >> 8; in alx_configure_basic()
978 pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN); in alx_configure_basic()
996 val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3; in alx_configure_basic()
999 val = (val - ALX_MTU_STD_ALGN) >> 3; in alx_configure_basic()
1022 (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT; in alx_configure_basic()
1025 /* default multi-tx-q weights */ in alx_configure_basic()
1052 if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) || in alx_get_phy_info()
1053 alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1])) in alx_get_phy_info()
1063 hw->mdio.mmds = devs1 | devs2 << 16; in alx_get_phy_info()
1071 hw->stats.rx_ok += alx_read_mem32(hw, ALX_MIB_RX_OK); in alx_update_hw_stats()
1072 hw->stats.rx_bcast += alx_read_mem32(hw, ALX_MIB_RX_BCAST); in alx_update_hw_stats()
1073 hw->stats.rx_mcast += alx_read_mem32(hw, ALX_MIB_RX_MCAST); in alx_update_hw_stats()
1074 hw->stats.rx_pause += alx_read_mem32(hw, ALX_MIB_RX_PAUSE); in alx_update_hw_stats()
1075 hw->stats.rx_ctrl += alx_read_mem32(hw, ALX_MIB_RX_CTRL); in alx_update_hw_stats()
1076 hw->stats.rx_fcs_err += alx_read_mem32(hw, ALX_MIB_RX_FCS_ERR); in alx_update_hw_stats()
1077 hw->stats.rx_len_err += alx_read_mem32(hw, ALX_MIB_RX_LEN_ERR); in alx_update_hw_stats()
1078 hw->stats.rx_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BYTE_CNT); in alx_update_hw_stats()
1079 hw->stats.rx_runt += alx_read_mem32(hw, ALX_MIB_RX_RUNT); in alx_update_hw_stats()
1080 hw->stats.rx_frag += alx_read_mem32(hw, ALX_MIB_RX_FRAG); in alx_update_hw_stats()
1081 hw->stats.rx_sz_64B += alx_read_mem32(hw, ALX_MIB_RX_SZ_64B); in alx_update_hw_stats()
1082 hw->stats.rx_sz_127B += alx_read_mem32(hw, ALX_MIB_RX_SZ_127B); in alx_update_hw_stats()
1083 hw->stats.rx_sz_255B += alx_read_mem32(hw, ALX_MIB_RX_SZ_255B); in alx_update_hw_stats()
1084 hw->stats.rx_sz_511B += alx_read_mem32(hw, ALX_MIB_RX_SZ_511B); in alx_update_hw_stats()
1085 hw->stats.rx_sz_1023B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1023B); in alx_update_hw_stats()
1086 hw->stats.rx_sz_1518B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1518B); in alx_update_hw_stats()
1087 hw->stats.rx_sz_max += alx_read_mem32(hw, ALX_MIB_RX_SZ_MAX); in alx_update_hw_stats()
1088 hw->stats.rx_ov_sz += alx_read_mem32(hw, ALX_MIB_RX_OV_SZ); in alx_update_hw_stats()
1089 hw->stats.rx_ov_rxf += alx_read_mem32(hw, ALX_MIB_RX_OV_RXF); in alx_update_hw_stats()
1090 hw->stats.rx_ov_rrd += alx_read_mem32(hw, ALX_MIB_RX_OV_RRD); in alx_update_hw_stats()
1091 hw->stats.rx_align_err += alx_read_mem32(hw, ALX_MIB_RX_ALIGN_ERR); in alx_update_hw_stats()
1092 hw->stats.rx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BCCNT); in alx_update_hw_stats()
1093 hw->stats.rx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_MCCNT); in alx_update_hw_stats()
1094 hw->stats.rx_err_addr += alx_read_mem32(hw, ALX_MIB_RX_ERRADDR); in alx_update_hw_stats()
1097 hw->stats.tx_ok += alx_read_mem32(hw, ALX_MIB_TX_OK); in alx_update_hw_stats()
1098 hw->stats.tx_bcast += alx_read_mem32(hw, ALX_MIB_TX_BCAST); in alx_update_hw_stats()
1099 hw->stats.tx_mcast += alx_read_mem32(hw, ALX_MIB_TX_MCAST); in alx_update_hw_stats()
1100 hw->stats.tx_pause += alx_read_mem32(hw, ALX_MIB_TX_PAUSE); in alx_update_hw_stats()
1101 hw->stats.tx_exc_defer += alx_read_mem32(hw, ALX_MIB_TX_EXC_DEFER); in alx_update_hw_stats()
1102 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); in alx_update_hw_stats()
1103 hw->stats.tx_defer += alx_read_mem32(hw, ALX_MIB_TX_DEFER); in alx_update_hw_stats()
1104 hw->stats.tx_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BYTE_CNT); in alx_update_hw_stats()
1105 hw->stats.tx_sz_64B += alx_read_mem32(hw, ALX_MIB_TX_SZ_64B); in alx_update_hw_stats()
1106 hw->stats.tx_sz_127B += alx_read_mem32(hw, ALX_MIB_TX_SZ_127B); in alx_update_hw_stats()
1107 hw->stats.tx_sz_255B += alx_read_mem32(hw, ALX_MIB_TX_SZ_255B); in alx_update_hw_stats()
1108 hw->stats.tx_sz_511B += alx_read_mem32(hw, ALX_MIB_TX_SZ_511B); in alx_update_hw_stats()
1109 hw->stats.tx_sz_1023B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1023B); in alx_update_hw_stats()
1110 hw->stats.tx_sz_1518B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1518B); in alx_update_hw_stats()
1111 hw->stats.tx_sz_max += alx_read_mem32(hw, ALX_MIB_TX_SZ_MAX); in alx_update_hw_stats()
1112 hw->stats.tx_single_col += alx_read_mem32(hw, ALX_MIB_TX_SINGLE_COL); in alx_update_hw_stats()
1113 hw->stats.tx_multi_col += alx_read_mem32(hw, ALX_MIB_TX_MULTI_COL); in alx_update_hw_stats()
1114 hw->stats.tx_late_col += alx_read_mem32(hw, ALX_MIB_TX_LATE_COL); in alx_update_hw_stats()
1115 hw->stats.tx_abort_col += alx_read_mem32(hw, ALX_MIB_TX_ABORT_COL); in alx_update_hw_stats()
1116 hw->stats.tx_underrun += alx_read_mem32(hw, ALX_MIB_TX_UNDERRUN); in alx_update_hw_stats()
1117 hw->stats.tx_trd_eop += alx_read_mem32(hw, ALX_MIB_TX_TRD_EOP); in alx_update_hw_stats()
1118 hw->stats.tx_len_err += alx_read_mem32(hw, ALX_MIB_TX_LEN_ERR); in alx_update_hw_stats()
1119 hw->stats.tx_trunc += alx_read_mem32(hw, ALX_MIB_TX_TRUNC); in alx_update_hw_stats()
1120 hw->stats.tx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BCCNT); in alx_update_hw_stats()
1121 hw->stats.tx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_MCCNT); in alx_update_hw_stats()
1123 hw->stats.update += alx_read_mem32(hw, ALX_MIB_UPDATE); in alx_update_hw_stats()