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/linux-6.12.1/drivers/gpu/drm/display/
Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
88 ld 8,8(4)
96 mulld 24,8,6
97 mulhdu 25,8,6
[all …]
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
Daes-spe-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "aes-spe-regs.h"
17 rlwimi rT0,in,28-((bpos+3)%4)*8,20,27;
20 rlwimi rT1,in,24-((bpos+3)%4)*8,24,31;
41 LBZ(out, rT0, 8)
44 LBZ(out, rT0, 8) /* load enc byte */
56 * via bl/blr. It expects that caller has pre-xored input data with first
57 * 4 words of encryption key into rD0-rD3. Pointer/counter registers must
58 * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
59 * and rW0-rW3 and caller must execute a final xor on the output registers.
[all …]
/linux-6.12.1/drivers/pmdomain/mediatek/
Dmt8195-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
10 #include "mtk-pm-domains.h"
11 #include <dt-bindings/power/mt8195-power.h>
24 .sram_pdn_bits = GENMASK(8, 8),
25 .sram_pdn_ack_bits = GENMASK(12, 12),
41 .sta_mask = BIT(12),
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
90 .sram_pdn_bits = GENMASK(8, 8),
[all …]
Dmt8192-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8192-power.h>
20 .sram_pdn_bits = GENMASK(8, 8),
21 .sram_pdn_ack_bits = GENMASK(12, 12),
63 .sram_pdn_bits = GENMASK(8, 8),
64 .sram_pdn_ack_bits = GENMASK(12, 12),
73 .sram_pdn_bits = GENMASK(8, 8),
74 .sram_pdn_ack_bits = GENMASK(12, 12),
105 .sram_pdn_bits = GENMASK(8, 8),
[all …]
Dmt8183-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8183-power.h>
20 .sram_pdn_bits = GENMASK(11, 8),
21 .sram_pdn_ack_bits = GENMASK(15, 12),
55 .sram_pdn_bits = GENMASK(8, 8),
56 .sram_pdn_ack_bits = GENMASK(12, 12),
65 .sram_pdn_bits = GENMASK(8, 8),
66 .sram_pdn_ack_bits = GENMASK(12, 12),
74 .sram_pdn_bits = GENMASK(8, 8),
[all …]
/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra234.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
1382 #define PINGROUP_REG_N(r) -1
1385 #define DRV_PINGROUP_N(r) -1
1388 .drv_reg = -1, \
1389 .drv_bank = -1, \
1390 .drvdn_bit = -1, \
1391 .drvup_bit = -1, \
1392 .slwr_bit = -1, \
[all …]
Dpinctrl-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
23 #include "pinctrl-tegra.h"
1281 #define PINGROUP_REG_N(r) -1
1284 #define DRV_PINGROUP_N(r) -1
1287 .drv_reg = -1, \
1288 .drv_bank = -1, \
1289 .drvdn_bit = -1, \
1290 .drvup_bit = -1, \
1291 .slwr_bit = -1, \
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
65 { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
67 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
68 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
76 { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
78 { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
80 { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
82 { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
84 { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dsc/
Drc_calc_fpu.c31 #define table_hash(mode, bpc, max_min) ((mode << 16) | (bpc << 8) | max_min)
57 num = num - 0.5; in dsc_roundf()
76 TABLE_CASE(444, 8, max); in get_qp_set()
77 TABLE_CASE(444, 8, min); in get_qp_set()
80 TABLE_CASE(444, 12, max); in get_qp_set()
81 TABLE_CASE(444, 12, min); in get_qp_set()
82 TABLE_CASE(422, 8, max); in get_qp_set()
83 TABLE_CASE(422, 8, min); in get_qp_set()
86 TABLE_CASE(422, 12, max); in get_qp_set()
87 TABLE_CASE(422, 12, min); in get_qp_set()
[all …]
/linux-6.12.1/arch/arm/mach-davinci/
Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
47 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
49 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
50 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
51 MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
52 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
[all …]
Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
7 * Derived from: arch/arm/mach-davinci/da830.c
16 #include <linux/mfd/da8xx-cfgchip.h>
20 #include <clocksource/timer-davinci.h>
61 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
62 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
64 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
65 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap3-echo.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
18 cpu0-supply = <&vdd1_reg>;
28 compatible = "regulator-fixed";
29 regulator-name = "vcc5v";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt5677.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5677.h -- RT5677 ALSA SoC audio driver
20 /* I/O - Output */
22 /* I/O - Input */
25 /* I/O - SLIMBus */
31 /* I/O - ADC/DAC */
43 /* Mixer - D-D */
60 /* Mixer - PDM */
116 /* Format - ADC/DAC */
124 /* Function - Analog */
[all …]
Drt5640.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
[all …]
Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
[all …]
Drt5682s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5682s.h -- RT5682I-VS ALSA SoC audio driver
17 #include <linux/clk-provider.h>
25 /* I/O - Output */
33 /* I/O - Input */
44 /* I/O - ADC/DAC/DMIC */
50 /* Mixer - D-D */
57 /* Mixer - ADC */
84 /* Format - ADC/DAC */
91 /* Format - TDM Control */
[all …]
Drt5665.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
[all …]
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt2712.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
33 MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
[all …]
Dpinctrl-mt8167.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8167.h"
18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
21 MTK_DRV_GRP(2, 8, 1, 2, 2),
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
36 MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
40 MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
[all …]
Dpinctrl-mt8516.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8516.h"
18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
21 MTK_DRV_GRP(2, 8, 1, 2, 2),
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
36 MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
40 MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
[all …]
/linux-6.12.1/lib/crypto/
Dchacha.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 WARN_ON_ONCE(nrounds != 20 && nrounds != 12); in chacha_permute()
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
35 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 8); in chacha_permute()
36 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 8); in chacha_permute()
[all …]
/linux-6.12.1/arch/x86/math-emu/
Dmul_Xsig.S1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*---------------------------------------------------------------------------+
5 | Multiply a 12 byte fixed point number by another fixed point number. |
9 | Australia. E-mail billm@jacobi.maths.monash.edu.au |
21 +---------------------------------------------------------------------------*/
38 movl %eax,-4(%ebp)
39 movl %eax,-8(%ebp)
43 movl %edx,-12(%ebp)
47 addl %eax,-12(%ebp)
48 adcl %edx,-8(%ebp)
[all …]
/linux-6.12.1/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
28 #define DA_CKM_XTAL_CK_FORCE_EN BIT(8)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
65 #define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)
66 #define DP_TX1_VOLT_SWING_SHIFT 8
[all …]

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