Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5677.h -- RT5677 ALSA SoC audio driver
20 /* I/O - Output */
22 /* I/O - Input */
25 /* I/O - SLIMBus */
31 /* I/O - ADC/DAC */
43 /* Mixer - D-D */
60 /* Mixer - PDM */
116 /* Format - ADC/DAC */
124 /* Function - Analog */
159 /* Function - Digital */
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
319 #define RT5677_LOUT2_L_DF_SFT (12)
326 #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
327 #define RT5677_LOUT2_ENH_DRV_SFT (8)
332 #define RT5677_BST_MASK1 (0xf << 12)
333 #define RT5677_BST_SFT1 12
334 #define RT5677_BST_MASK2 (0xf << 8)
335 #define RT5677_BST_SFT2 8
377 #define RT5677_ST_HPF_PATH (0x1 << 12)
378 #define RT5677_ST_HPF_PATH_SFT 12
397 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
398 #define RT5677_SEL_DAC4_L_SRC_SFT 12
401 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
402 #define RT5677_SEL_DAC4_R_SRC_SFT 8
413 #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
414 #define RT5677_DAC4_L_VOL_SFT 8
419 #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
420 #define RT5677_DAC3_L_VOL_SFT 8
425 #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
426 #define RT5677_DAC1_L_VOL_SFT 8
431 #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
432 #define RT5677_DAC2_L_VOL_SFT 8
461 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
462 #define RT5677_STO1_ADC_R_BST_SFT 12
465 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
466 #define RT5677_STO2_ADC_L_BST_SFT 8
473 #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
474 #define RT5677_STO2_ADC_L_VOL_SFT 8
481 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
482 #define RT5677_MONO_ADC_R_BST_SFT 12
489 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
490 #define RT5677_STO3_ADC_R_BST_SFT 12
493 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
494 #define RT5677_STO4_ADC_L_BST_SFT 8
501 #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
502 #define RT5677_STO3_ADC_L_VOL_SFT 8
507 #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
508 #define RT5677_STO4_ADC_L_VOL_SFT 8
517 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
518 #define RT5677_SEL_STO4_ADC1_SFT 12
521 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
522 #define RT5677_SEL_STO4_DMIC_SFT 8
533 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
534 #define RT5677_SEL_STO3_ADC1_SFT 12
537 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
538 #define RT5677_SEL_STO3_DMIC_SFT 8
549 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
550 #define RT5677_SEL_STO2_ADC1_SFT 12
553 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
554 #define RT5677_SEL_STO2_DMIC_SFT 8
569 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
570 #define RT5677_SEL_STO1_ADC1_SFT 12
573 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
574 #define RT5677_SEL_STO1_DMIC_SFT 8
585 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
586 #define RT5677_SEL_MONO_ADC_L1_SFT 12
589 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
590 #define RT5677_SEL_MONO_DMIC_L_SFT 8
607 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
608 #define RT5677_DAC1_L_SEL_SFT 8
621 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
622 #define RT5677_DAC1_L_STO_L_VOL_SFT 12
629 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
630 #define RT5677_DAC1_R_STO_L_VOL_SFT 8
651 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
652 #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
659 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
660 #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
683 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
684 #define RT5677_MONO_L_DD1_L_VOL_SFT 12
691 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
692 #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
717 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
718 #define RT5677_MONO_L_DD2_L_VOL_SFT 12
725 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
726 #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
763 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
764 #define RT5677_SEL_PDM1_L_SFT 12
767 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
768 #define RT5677_SEL_PDM1_R_SFT 8
788 #define RT5677_PDM1_I2C_ID (0xf << 12)
792 #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
800 #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)
801 #define RT5677_IF1_ADC_MODE_SFT 12
802 #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12)
803 #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)
816 #define RT5677_IF1_ADC3_MASK (0x3 << 8)
817 #define RT5677_IF1_ADC3_SFT 8
826 #define RT5677_IF1_DAC0_MASK (0x7 << 12)
827 #define RT5677_IF1_DAC0_SFT 12
828 #define RT5677_IF1_DAC1_MASK (0x7 << 8)
829 #define RT5677_IF1_DAC1_SFT 8
836 #define RT5677_IF1_DAC4_MASK (0x7 << 12)
837 #define RT5677_IF1_DAC4_SFT 12
838 #define RT5677_IF1_DAC5_MASK (0x7 << 8)
839 #define RT5677_IF1_DAC5_SFT 8
846 #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)
847 #define RT5677_IF2_ADC_MODE_SFT 12
848 #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12)
849 #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)
862 #define RT5677_IF2_ADC3_MASK (0x3 << 8)
863 #define RT5677_IF2_ADC3_SFT 8
872 #define RT5677_IF2_DAC0_MASK (0x7 << 12)
873 #define RT5677_IF2_DAC0_SFT 12
874 #define RT5677_IF2_DAC1_MASK (0x7 << 8)
875 #define RT5677_IF2_DAC1_SFT 8
882 #define RT5677_IF2_DAC4_MASK (0x7 << 12)
883 #define RT5677_IF2_DAC4_SFT 12
884 #define RT5677_IF2_DAC5_MASK (0x7 << 8)
885 #define RT5677_IF2_DAC5_SFT 8
904 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
905 #define RT5677_DMIC_R_STO1_LH_SFT 12
906 #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
907 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
920 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
921 #define RT5677_DMIC_R_STO2_LH_SFT 8
922 #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
923 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
988 #define RT5677_PWR_DAC1 (0x1 << 12)
989 #define RT5677_PWR_DAC1_BIT 12
1016 #define RT5677_PWR_DAC_S1F (0x1 << 12)
1017 #define RT5677_PWR_DAC_S1F_BIT 12
1024 #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
1025 #define RT5677_PWR_DAC_M3F_R_BIT 8
1048 #define RT5677_PWR_LO1 (0x1 << 12)
1049 #define RT5677_PWR_LO1_BIT 12
1056 #define RT5677_PWR_VREF2 (0x1 << 8)
1057 #define RT5677_PWR_VREF2_BIT 8
1072 #define RT5677_PWR_SLIM (0x1 << 12)
1073 #define RT5677_PWR_SLIM_BIT 12
1080 #define RT5677_PWR_PLL2 (0x1 << 8)
1081 #define RT5677_PWR_PLL2_BIT 8
1102 #define RT5677_PWR_SR5 (0x1 << 8)
1103 #define RT5677_PWR_SR5_BIT 8
1124 #define RT5677_PWR_SR6_RDY (0x1 << 8)
1125 #define RT5677_PWR_SR6_RDY_BIT 8
1150 #define RT5677_PWR_SR7_ISO (0x1 << 8)
1151 #define RT5677_PWR_SR7_ISO_BIT 8
1179 #define RT5677_I2S_I_CP_MASK (0x3 << 8)
1180 #define RT5677_I2S_I_CP_SFT 8
1181 #define RT5677_I2S_I_CP_OFF (0x0 << 8)
1182 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1183 #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1202 #define RT5677_I2S_PD1_MASK (0x7 << 12)
1203 #define RT5677_I2S_PD1_SFT 12
1204 #define RT5677_I2S_PD1_1 (0x0 << 12)
1205 #define RT5677_I2S_PD1_2 (0x1 << 12)
1206 #define RT5677_I2S_PD1_3 (0x2 << 12)
1207 #define RT5677_I2S_PD1_4 (0x3 << 12)
1208 #define RT5677_I2S_PD1_6 (0x4 << 12)
1209 #define RT5677_I2S_PD1_8 (0x5 << 12)
1210 #define RT5677_I2S_PD1_12 (0x6 << 12)
1211 #define RT5677_I2S_PD1_16 (0x7 << 12)
1216 #define RT5677_I2S_PD2_MASK (0x7 << 8)
1217 #define RT5677_I2S_PD2_SFT 8
1218 #define RT5677_I2S_PD2_1 (0x0 << 8)
1219 #define RT5677_I2S_PD2_2 (0x1 << 8)
1220 #define RT5677_I2S_PD2_3 (0x2 << 8)
1221 #define RT5677_I2S_PD2_4 (0x3 << 8)
1222 #define RT5677_I2S_PD2_6 (0x4 << 8)
1223 #define RT5677_I2S_PD2_8 (0x5 << 8)
1224 #define RT5677_I2S_PD2_12 (0x6 << 8)
1225 #define RT5677_I2S_PD2_16 (0x7 << 8)
1256 #define RT5677_I2S_PD5_MASK (0x7 << 12)
1257 #define RT5677_I2S_PD5_SFT 12
1258 #define RT5677_I2S_PD5_1 (0x0 << 12)
1259 #define RT5677_I2S_PD5_2 (0x1 << 12)
1260 #define RT5677_I2S_PD5_3 (0x2 << 12)
1261 #define RT5677_I2S_PD5_4 (0x3 << 12)
1262 #define RT5677_I2S_PD5_6 (0x4 << 12)
1263 #define RT5677_I2S_PD5_8 (0x5 << 12)
1264 #define RT5677_I2S_PD5_12 (0x6 << 12)
1265 #define RT5677_I2S_PD5_16 (0x7 << 12)
1266 #define RT5677_I2S_PD6_MASK (0x7 << 8)
1267 #define RT5677_I2S_PD6_SFT 8
1268 #define RT5677_I2S_PD6_1 (0x0 << 8)
1269 #define RT5677_I2S_PD6_2 (0x1 << 8)
1270 #define RT5677_I2S_PD6_3 (0x2 << 8)
1271 #define RT5677_I2S_PD6_4 (0x3 << 8)
1272 #define RT5677_I2S_PD6_6 (0x4 << 8)
1273 #define RT5677_I2S_PD6_8 (0x5 << 8)
1274 #define RT5677_I2S_PD6_12 (0x6 << 8)
1275 #define RT5677_I2S_PD6_16 (0x7 << 8)
1335 #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1336 #define RT5677_PLL_M_SFT 12
1362 #define RT5677_PLL1_PD_MASK (0x1 << 8)
1363 #define RT5677_PLL1_PD_SFT 8
1364 #define RT5677_PLL1_PD_1 (0x0 << 8)
1365 #define RT5677_PLL1_PD_2 (0x1 << 8)
1382 #define RT5677_PLL2_SRC_MASK (0x7 << 12)
1383 #define RT5677_PLL2_SRC_SFT 12
1384 #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1385 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1386 #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1387 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1388 #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1389 #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1390 #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1397 #define RT5677_DSP_ASRC_I_SRC (0x3 << 8)
1398 #define RT5677_DSP_ASRC_I_SRC_SFT 8
1399 #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8)
1400 #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)
1401 #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8)
1402 #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)
1409 #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)
1410 #define RT5677_DA_STO_CLK_SEL_SFT 12
1417 #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)
1418 #define RT5677_DA_MONO3L_CLK_SEL_SFT 12
1419 #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)
1420 #define RT5677_DA_MONO3R_CLK_SEL_SFT 8
1427 #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)
1428 #define RT5677_AD_STO1_CLK_SEL_SFT 12
1429 #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)
1430 #define RT5677_AD_STO2_CLK_SEL_SFT 8
1437 #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)
1438 #define RT5677_AD_MONOL_CLK_SEL_SFT 12
1439 #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)
1440 #define RT5677_AD_MONOR_CLK_SEL_SFT 8
1443 #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)
1444 #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12
1445 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
1446 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
1448 /* ASRC Control 8 (0x8a) */
1449 #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)
1450 #define RT5677_I2S1_CLK_SEL_SFT 12
1451 #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)
1452 #define RT5677_I2S2_CLK_SEL_SFT 8
1465 #define RT5677_VAD_BUF_OW (1 << 8)
1466 #define RT5677_VAD_BUF_OW_BIT 8
1485 #define RT5677_VAD_SRC_MASK (0x3 << 8)
1486 #define RT5677_VAD_SRC_SFT 8
1491 #define RT5677_IB01_SRC_MASK (0x7 << 12)
1492 #define RT5677_IB01_SRC_SFT 12
1493 #define RT5677_IB23_SRC_MASK (0x7 << 8)
1494 #define RT5677_IB23_SRC_SFT 8
1501 #define RT5677_IB7_SRC_MASK (0x7 << 12)
1502 #define RT5677_IB7_SRC_SFT 12
1503 #define RT5677_IB8_SRC_MASK (0x7 << 8)
1504 #define RT5677_IB8_SRC_SFT 8
1523 #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
1524 #define RT5677_SEL_GPIO_JD2_SFT 12
1535 #define RT5677_INV_GPIO_JD1 (0x1 << 12)
1536 #define RT5677_INV_GPIO_JD1_SFT 12
1543 #define RT5677_INV_GPIO_JD2 (0x1 << 8)
1544 #define RT5677_INV_GPIO_JD2_SFT 8
1617 #define RT5677_DSP_IB_6_H (0x1 << 12)
1618 #define RT5677_DSP_IB_6_H_SFT 12
1725 RT5677_AD_STEREO2_FILTER = (0x1 << 8),
1729 RT5677_AD_MONO_R_FILTER = (0x1 << 12),
1753 /* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */