Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
112 /* Format - ADC/DAC */
120 /* Format - TDM Control */
129 /* Function - Analog */
158 /* Function - Digital */
439 #define RT5665_L_VOL_MASK (0x3f << 8)
440 #define RT5665_L_VOL_SFT 8
445 #define RT5665_G_HP (0xf << 8)
446 #define RT5665_G_HP_SFT 8
451 #define RT5665_BST_CBJ_MASK (0xf << 8)
452 #define RT5665_BST_CBJ_SFT 8
457 #define RT5665_BST1_MASK (0x7f << 8)
458 #define RT5665_BST1_SFT 8
467 #define RT5665_BST3_MASK (0x7f << 8)
468 #define RT5665_BST3_SFT 8
475 #define RT5665_INL_VOL_MASK (0x1f << 8)
476 #define RT5665_INL_VOL_SFT 8
489 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
490 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
491 #define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
517 #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
518 #define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
519 #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
532 #define RT5665_M_DAC2_R_VOL (0x1 << 12)
533 #define RT5665_M_DAC2_R_VOL_SFT 12
546 #define RT5665_DAC_L1_VOL_MASK (0xff << 8)
547 #define RT5665_DAC_L1_VOL_SFT 8
552 #define RT5665_DAC_L2_VOL_MASK (0xff << 8)
553 #define RT5665_DAC_L2_VOL_SFT 8
560 #define RT5665_M_DAC3_R_VOL (0x1 << 12)
561 #define RT5665_M_DAC3_R_VOL_SFT 12
568 #define RT5665_ADC_L_VOL_MASK (0x7f << 8)
569 #define RT5665_ADC_L_VOL_SFT 8
574 #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
575 #define RT5665_MONO_ADC_L_VOL_SFT 8
582 #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
583 #define RT5665_STO1_ADC_R_BST_SFT 12
588 #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
589 #define RT5665_MONO_ADC_R_BST_SFT 12
594 #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
595 #define RT5665_STO2_ADC_R_BST_SFT 12
606 #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
607 #define RT5665_STO1_ADC2L_SRC_SFT 12
612 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
613 #define RT5665_STO1_DMIC_SRC_SFT 8
614 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
615 #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
637 #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
638 #define RT5665_MONO_ADC_L2_SRC_SFT 12
643 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
644 #define RT5665_MONO_DMIC_L_SRC_SFT 8
670 #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
671 #define RT5665_STO2_ADC2L_SRC_SFT 12
676 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
677 #define RT5665_STO2_DMIC_SRC_SFT 8
678 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
679 #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
701 #define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
702 #define RT5665_DAC1_L_SEL_SFT 8
715 #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
716 #define RT5665_G_DAC_R1_STO_L_SFT 12
723 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
724 #define RT5665_G_DAC_R2_STO_L_SFT 8
749 #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
750 #define RT5665_G_DAC_R1_MONO_L_SFT 12
757 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
758 #define RT5665_G_DAC_R2_MONO_L_SFT 8
783 #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
784 #define RT5665_G_DAC_L2_STO2_L_SFT 12
791 #define RT5665_M_ST_DAC_R1 (0x1 << 8)
792 #define RT5665_M_ST_DAC_R1_SFT 8
807 #define RT5665_DAC_MIX_L_MASK (0x3 << 12)
808 #define RT5665_DAC_MIX_L_SFT 12
809 #define RT5665_DAC_MIX_R_MASK (0x3 << 8)
810 #define RT5665_DAC_MIX_R_SFT 8
823 #define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
824 #define RT5665_IF2_1_ADC_IN_SFT 12
827 #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
828 #define RT5665_IF2_1_ADC_SEL_SFT 8
847 #define RT5665_M_PDM1_R (0x1 << 12)
848 #define RT5665_M_PDM1_R_SFT 12
851 #define RT5665_PDM1_R_MASK (0x3 << 8)
852 #define RT5665_PDM1_R_SFT 8
954 #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
955 #define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
958 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
959 #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
966 #define RT5665_M_DAC_L2_MA (0x1 << 8)
967 #define RT5665_M_DAC_L2_MA_SFT 8
980 #define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
981 #define RT5665_G_BST3_OM_L_SFT 12
1022 #define RT5665_M_OV_R_LM (0x1 << 12)
1023 #define RT5665_M_OV_R_LM_SFT 12
1035 #define RT5665_PWR_I2S2_2 (0x1 << 12)
1036 #define RT5665_PWR_I2S2_2_BIT 12
1043 #define RT5665_PWR_LDO (0x1 << 8)
1044 #define RT5665_PWR_LDO_BIT 8
1065 #define RT5665_PWR_ADC_MF_R (0x1 << 12)
1066 #define RT5665_PWR_ADC_MF_R_BIT 12
1073 #define RT5665_PWR_DAC_MF_R (0x1 << 8)
1074 #define RT5665_PWR_DAC_MF_R_BIT 8
1085 #define RT5665_PWR_FV2 (0x1 << 12)
1086 #define RT5665_PWR_FV2_BIT 12
1093 #define RT5665_PWR_LM (0x1 << 8)
1094 #define RT5665_PWR_LM_BIT 8
1120 #define RT5665_PWR_BST4 (0x1 << 12)
1121 #define RT5665_PWR_BST4_BIT 12
1150 #define RT5665_PWR_BST_L (0x1 << 8)
1151 #define RT5665_PWR_BST_L_BIT 8
1168 #define RT5665_PWR_OM_R (0x1 << 12)
1169 #define RT5665_PWR_OM_R_BIT 12
1190 #define RT5665_PWR_OV_R (0x1 << 12)
1191 #define RT5665_PWR_OV_R_BIT 12
1194 #define RT5665_PWR_IN_R (0x1 << 8)
1195 #define RT5665_PWR_IN_R_BIT 8
1205 #define RT5665_LOUT_CLK_DET 12
1256 #define RT5665_I2S_BP_MASK (0x1 << 8)
1257 #define RT5665_I2S_BP_SFT 8
1258 #define RT5665_I2S_BP_NOR (0x0 << 8)
1259 #define RT5665_I2S_BP_INV (0x1 << 8)
1276 #define RT5665_I2S_PD1_MASK (0x7 << 12)
1277 #define RT5665_I2S_PD1_SFT 12
1278 #define RT5665_I2S_PD1_1 (0x0 << 12)
1279 #define RT5665_I2S_PD1_2 (0x1 << 12)
1280 #define RT5665_I2S_PD1_3 (0x2 << 12)
1281 #define RT5665_I2S_PD1_4 (0x3 << 12)
1282 #define RT5665_I2S_PD1_6 (0x4 << 12)
1283 #define RT5665_I2S_PD1_8 (0x5 << 12)
1284 #define RT5665_I2S_PD1_12 (0x6 << 12)
1285 #define RT5665_I2S_PD1_16 (0x7 << 12)
1286 #define RT5665_I2S_M_PD2_MASK (0x7 << 8)
1287 #define RT5665_I2S_M_PD2_SFT 8
1288 #define RT5665_I2S_M_PD2_1 (0x0 << 8)
1289 #define RT5665_I2S_M_PD2_2 (0x1 << 8)
1290 #define RT5665_I2S_M_PD2_3 (0x2 << 8)
1291 #define RT5665_I2S_M_PD2_4 (0x3 << 8)
1292 #define RT5665_I2S_M_PD2_6 (0x4 << 8)
1293 #define RT5665_I2S_M_PD2_8 (0x5 << 8)
1294 #define RT5665_I2S_M_PD2_12 (0x6 << 8)
1295 #define RT5665_I2S_M_PD2_16 (0x7 << 8)
1317 #define RT5665_I2S_PD2_MASK (0x7 << 12)
1318 #define RT5665_I2S_PD2_SFT 12
1319 #define RT5665_I2S_PD2_1 (0x0 << 12)
1320 #define RT5665_I2S_PD2_2 (0x1 << 12)
1321 #define RT5665_I2S_PD2_3 (0x2 << 12)
1322 #define RT5665_I2S_PD2_4 (0x3 << 12)
1323 #define RT5665_I2S_PD2_6 (0x4 << 12)
1324 #define RT5665_I2S_PD2_8 (0x5 << 12)
1325 #define RT5665_I2S_PD2_12 (0x6 << 12)
1326 #define RT5665_I2S_PD2_16 (0x7 << 12)
1331 #define RT5665_I2S_PD3_MASK (0x7 << 8)
1332 #define RT5665_I2S_PD3_SFT 8
1333 #define RT5665_I2S_PD3_1 (0x0 << 8)
1334 #define RT5665_I2S_PD3_2 (0x1 << 8)
1335 #define RT5665_I2S_PD3_3 (0x2 << 8)
1336 #define RT5665_I2S_PD3_4 (0x3 << 8)
1337 #define RT5665_I2S_PD3_6 (0x4 << 8)
1338 #define RT5665_I2S_PD3_8 (0x5 << 8)
1339 #define RT5665_I2S_PD3_12 (0x6 << 8)
1340 #define RT5665_I2S_PD3_16 (0x7 << 8)
1361 #define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
1362 #define RT5665_TDM_OUT_CH_2 (0x0 << 8)
1363 #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1364 #define RT5665_TDM_OUT_CH_6 (0x2 << 8)
1365 #define RT5665_TDM_OUT_CH_8 (0x3 << 8)
1380 #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
1382 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
1391 #define RT5665_IF1_ADC3_SEL_SFT 8
1403 #define RT5665_PLL1_SRC_MASK (0x7 << 8)
1404 #define RT5665_PLL1_SRC_SFT 8
1405 #define RT5665_PLL1_SRC_MCLK (0x0 << 8)
1406 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1407 #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
1408 #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
1425 #define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
1426 #define RT5665_PLL_M_SFT 12
1439 #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
1440 #define RT5665_DAC_STO1_ASRC_SFT 12
1447 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1448 #define RT5665_DMIC_STO1_ASRC_SFT 8
1465 #define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
1466 #define RT5665_DA_STO1_CLK_SEL_SFT 12
1467 #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
1468 #define RT5665_DA_STO2_CLK_SEL_SFT 8
1475 #define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
1476 #define RT5665_AD_STO1_CLK_SEL_SFT 12
1477 #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
1478 #define RT5665_AD_STO2_CLK_SEL_SFT 8
1485 #define RT5665_I2S1_RATE_MASK (0xf << 12)
1486 #define RT5665_I2S1_RATE_SFT 12
1487 #define RT5665_I2S2_RATE_MASK (0xf << 8)
1488 #define RT5665_I2S2_RATE_SFT 8
1500 #define RT5665_RAMP_MASK (0x1 << 12)
1501 #define RT5665_RAMP_SFT 12
1502 #define RT5665_RAMP_DIS (0x0 << 12)
1503 #define RT5665_RAMP_EN (0x1 << 12)
1512 #define RT5665_MRES_MASK (0x3 << 8)
1513 #define RT5665_MRES_SFT 8
1514 #define RT5665_MRES_15MO (0x0 << 8)
1515 #define RT5665_MRES_25MO (0x1 << 8)
1516 #define RT5665_MRES_35MO (0x2 << 8)
1517 #define RT5665_MRES_45MO (0x3 << 8)
1530 #define RT5665_CP_SYS_MASK (0x7 << 12)
1531 #define RT5665_CP_SYS_SFT 12
1532 #define RT5665_CP_FQ1_MASK (0x7 << 8)
1533 #define RT5665_CP_FQ1_SFT 8
1556 #define RT5665_PM_HP_MASK (0x3 << 8)
1557 #define RT5665_PM_HP_SFT 8
1558 #define RT5665_PM_HP_LV (0x0 << 8)
1559 #define RT5665_PM_HP_MV (0x1 << 8)
1560 #define RT5665_PM_HP_HV (0x2 << 8)
1591 #define RT5665_MIC2_CLK_MASK (0x1 << 12)
1592 #define RT5665_MIC2_CLK_SFT 12
1593 #define RT5665_MIC2_CLK_DIS (0x0 << 12)
1594 #define RT5665_MIC2_CLK_EN (0x1 << 12)
1604 #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1605 #define RT5665_MIC2_OVCD_SFT 8
1606 #define RT5665_MIC2_OVCD_DIS (0x0 << 8)
1607 #define RT5665_MIC2_OVCD_EN (0x1 << 8)
1623 #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1624 #define RT5665_PWR_CLK1M_SFT 8
1625 #define RT5665_PWR_CLK1M_PD (0x0 << 8)
1626 #define RT5665_PWR_CLK1M_PU (0x1 << 8)
1640 #define RT5665_I2S2_SRC_MASK (0x3 << 12)
1641 #define RT5665_I2S2_SRC_SFT 12
1642 #define RT5665_I2S2_M_PD_MASK (0x7 << 8)
1643 #define RT5665_I2S2_M_PD_SFT 8
1659 #define RT5665_EQ_DITH_MASK (0x3 << 8)
1660 #define RT5665_EQ_DITH_SFT 8
1661 #define RT5665_EQ_DITH_NOR (0x0 << 8)
1662 #define RT5665_EQ_DITH_LSB (0x1 << 8)
1663 #define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
1664 #define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
1671 #define RT5665_JD1_2_EN_MASK (0x1 << 12)
1672 #define RT5665_JD1_2_EN_SFT 12
1673 #define RT5665_JD1_2_DIS (0x0 << 12)
1674 #define RT5665_JD1_2_EN (0x1 << 12)
1735 #define RT5665_GP10_PIN_MASK (0x3 << 12)
1736 #define RT5665_GP10_PIN_SFT 12
1737 #define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
1738 #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
1739 #define RT5665_GP10_PIN_LPD (0x2 << 12)
1749 #define RT5665_GP2_OUT_MASK (0x1 << 8)
1750 #define RT5665_GP2_OUT_H (0x0 << 8)
1751 #define RT5665_GP2_OUT_L (0x1 << 8)
1788 #define RT5665_GP8_OUT_MASK (0x1 << 12)
1789 #define RT5665_GP8_OUT_H (0x0 << 12)
1790 #define RT5665_GP8_OUT_L (0x1 << 12)
1800 #define RT5665_GP10_OUT_MASK (0x1 << 8)
1801 #define RT5665_GP10_OUT_H (0x0 << 8)
1802 #define RT5665_GP10_OUT_L (0x1 << 8)
1819 #define RT5665_HP_SV_MASK (0x1 << 12)
1820 #define RT5665_HP_SV_SFT 12
1821 #define RT5665_HP_SV_DIS (0x0 << 12)
1822 #define RT5665_HP_SV_EN (0x1 << 12)
1873 #define RT5665_M_RF_DIG_MASK (0x1 << 12)
1874 #define RT5665_M_RF_DIG_SFT 12
1880 #define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
1881 #define RT5665_CKGEN_DAC1_SFT 12
1890 #define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
1891 #define RT5665_CKGEN_ADC1_SFT 12
1925 #define RT5665_SAR_POW_MASK (0x1 << 12)
1926 #define RT5665_SAR_POW_EN (0x1 << 12)
1927 #define RT5665_SAR_POW_DIS (0x0 << 12)
1937 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1938 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1939 #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)