Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
84 /* Function - Analog */
102 /* Function - Digital */
191 #define RT5640_L_VOL_MASK (0x3f << 8)
192 #define RT5640_L_VOL_SFT 8
205 #define RT5640_BST_SFT1 12
206 #define RT5640_BST_SFT2 8
217 #define RT5640_INL_VOL_MASK (0x1f << 8)
218 #define RT5640_INL_VOL_SFT 8
227 #define RT5640_DAC_L1_VOL_MASK (0xff << 8)
228 #define RT5640_DAC_L1_VOL_SFT 8
233 #define RT5640_DAC_L2_VOL_MASK (0xff << 8)
234 #define RT5640_DAC_L2_VOL_SFT 8
241 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
242 #define RT5640_M_DAC_R2_VOL_SFT 12
245 #define RT5640_ADC_L_VOL_MASK (0x7f << 8)
246 #define RT5640_ADC_L_VOL_SFT 8
251 #define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
252 #define RT5640_MONO_ADC_L_VOL_SFT 8
259 #define RT5640_ADC_R_BST_MASK (0x3 << 12)
260 #define RT5640_ADC_R_BST_SFT 12
269 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
270 #define RT5640_ADC_1_SRC_SFT 12
271 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
272 #define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
288 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
289 #define RT5640_MONO_ADC_L1_SRC_SFT 12
290 #define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
291 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
326 #define RT5640_M_DAC_L2 (0x1 << 12)
327 #define RT5640_M_DAC_L2_SFT 12
348 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
349 #define RT5640_M_DAC_L2_MONO_L_SFT 12
376 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
377 #define RT5640_DAC_L2_DAC_L_VOL_SFT 12
384 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
385 #define RT5640_DAC_R2_DAC_R_VOL_SFT 8
404 #define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
405 #define RT5640_DAC_R2_SEL_SFT 12
406 #define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
407 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
408 #define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
417 #define RT5640_RXDC_SEL_MASK (0x3 << 8)
418 #define RT5640_RXDC_SEL_SFT 8
419 #define RT5640_RXDC_SEL_NOR (0x0 << 8)
420 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
421 #define RT5640_RXDC_SEL_R2L (0x2 << 8)
422 #define RT5640_RXDC_SEL_SWAP (0x3 << 8)
449 #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
450 #define RT5640_IF1_ADC_SEL_SFT 12
451 #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
452 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
453 #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
454 #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
461 #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
462 #define RT5640_IF2_ADC_SEL_SFT 8
463 #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
464 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
465 #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
466 #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
551 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
552 #define RT5640_G_HPOMIX_SFT 12
557 #define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
558 #define RT5640_G_IN_L_SM_L_SFT 12
561 #define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
562 #define RT5640_G_DAC_L2_SM_L_SFT 8
579 #define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
580 #define RT5640_G_IN_R_SM_R_SFT 12
583 #define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
584 #define RT5640_G_DAC_R2_SM_R_SFT 8
605 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
606 #define RT5640_M_SV_L_SPM_L_SFT 12
613 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
614 #define RT5640_M_SV_R_SPM_R_SFT 12
629 #define RT5640_M_OV_L_MM (0x1 << 12)
630 #define RT5640_M_OV_L_MM_SFT 12
657 #define RT5640_M_SM_L_OM_L (0x1 << 8)
658 #define RT5640_M_SM_L_OM_L_SFT 8
697 #define RT5640_M_SM_L_OM_R (0x1 << 8)
698 #define RT5640_M_SM_L_OM_R_SFT 8
723 #define RT5640_M_OV_R_LM (0x1 << 12)
724 #define RT5640_M_OV_R_LM_SFT 12
733 #define RT5640_PWR_DAC_L1 (0x1 << 12)
734 #define RT5640_PWR_DAC_L1_BIT 12
755 #define RT5640_PWR_I2S_DSP (0x1 << 12)
756 #define RT5640_PWR_I2S_DSP_BIT 12
765 #define RT5640_PWR_LM (0x1 << 12)
766 #define RT5640_PWR_LM_BIT 12
771 #define RT5640_PWR_MA (0x1 << 8)
772 #define RT5640_PWR_MA_BIT 8
793 #define RT5640_PWR_BST4 (0x1 << 12)
794 #define RT5640_PWR_BST4_BIT 12
807 #define RT5640_PWR_SM_R (0x1 << 12)
808 #define RT5640_PWR_SM_R_BIT 12
821 #define RT5640_PWR_OV_R (0x1 << 12)
822 #define RT5640_PWR_OV_R_BIT 12
829 #define RT5640_PWR_IN_R (0x1 << 8)
830 #define RT5640_PWR_IN_R_BIT 8
837 #define RT5640_I2S_IF_MASK (0x7 << 12)
838 #define RT5640_I2S_IF_SFT 12
844 #define RT5640_I2S_I_CP_MASK (0x3 << 8)
845 #define RT5640_I2S_I_CP_SFT 8
846 #define RT5640_I2S_I_CP_OFF (0x0 << 8)
847 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
848 #define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
877 #define RT5640_I2S_PD1_MASK (0x7 << 12)
878 #define RT5640_I2S_PD1_SFT 12
879 #define RT5640_I2S_PD1_1 (0x0 << 12)
880 #define RT5640_I2S_PD1_2 (0x1 << 12)
881 #define RT5640_I2S_PD1_3 (0x2 << 12)
882 #define RT5640_I2S_PD1_4 (0x3 << 12)
883 #define RT5640_I2S_PD1_6 (0x4 << 12)
884 #define RT5640_I2S_PD1_8 (0x5 << 12)
885 #define RT5640_I2S_PD1_12 (0x6 << 12)
886 #define RT5640_I2S_PD1_16 (0x7 << 12)
891 #define RT5640_I2S_PD2_MASK (0x7 << 8)
892 #define RT5640_I2S_PD2_SFT 8
893 #define RT5640_I2S_PD2_1 (0x0 << 8)
894 #define RT5640_I2S_PD2_2 (0x1 << 8)
895 #define RT5640_I2S_PD2_3 (0x2 << 8)
896 #define RT5640_I2S_PD2_4 (0x3 << 8)
897 #define RT5640_I2S_PD2_6 (0x4 << 8)
898 #define RT5640_I2S_PD2_8 (0x5 << 8)
899 #define RT5640_I2S_PD2_12 (0x6 << 8)
900 #define RT5640_I2S_PD2_16 (0x7 << 8)
935 #define RT5640_ADC_R_OSR_MASK (0x3 << 12)
936 #define RT5640_ADC_R_OSR_SFT 12
937 #define RT5640_ADC_R_OSR_128 (0x0 << 12)
938 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
939 #define RT5640_ADC_R_OSR_32 (0x2 << 12)
940 #define RT5640_ADC_R_OSR_16 (0x3 << 12)
959 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
960 #define RT5640_DMIC_1R_LH_SFT 12
961 #define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
962 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
975 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
976 #define RT5640_DMIC_2R_LH_SFT 8
977 #define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
978 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
988 #define RT5640_PLL1_SRC_MASK (0x3 << 12)
989 #define RT5640_PLL1_SRC_SFT 12
990 #define RT5640_PLL1_SRC_MCLK (0x0 << 12)
991 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
992 #define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
993 #define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
1011 #define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1012 #define RT5640_PLL_M_SFT 12
1025 #define RT5640_I2S2_F_MASK (0x1 << 12)
1026 #define RT5640_I2S2_F_SFT 12
1027 #define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1028 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1033 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1034 #define RT5640_DMIC_2_M_SFT 8
1035 #define RT5640_DMIC_2_M_NOR (0x0 << 8)
1036 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1055 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1056 #define RT5640_MAD_R_M_SFT 12
1057 #define RT5640_MAD_R_M_NOR (0x0 << 12)
1058 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1082 #define RT5640_I2S1_RATE_MASK (0xf << 12)
1083 #define RT5640_I2S1_RATE_SFT 12
1084 #define RT5640_I2S2_RATE_MASK (0xf << 8)
1085 #define RT5640_I2S2_RATE_SFT 8
1088 #define RT5640_I2S1_PD_MASK (0x7 << 12)
1089 #define RT5640_I2S1_PD_SFT 12
1090 #define RT5640_I2S2_PD_MASK (0x7 << 8)
1091 #define RT5640_I2S2_PD_SFT 8
1098 #define RT5640_HP_OC_TH_MASK (0x3 << 8)
1099 #define RT5640_HP_OC_TH_SFT 8
1100 #define RT5640_HP_OC_TH_90 (0x0 << 8)
1101 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1102 #define RT5640_HP_OC_TH_120 (0x2 << 8)
1103 #define RT5640_HP_OC_TH_135 (0x3 << 8)
1110 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1111 #define RT5640_AUTO_PD_SFT 8
1112 #define RT5640_AUTO_PD_DIS (0x0 << 8)
1113 #define RT5640_AUTO_PD_EN (0x1 << 8)
1118 #define RT5640_CLSD_RATIO_MASK (0xf << 12)
1119 #define RT5640_CLSD_RATIO_SFT 12
1138 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1139 #define RT5640_HP_R_SMT_SFT 8
1140 #define RT5640_HP_R_SMT_DIS (0x0 << 8)
1141 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1180 #define RT5640_RAMP_MASK (0x1 << 12)
1181 #define RT5640_RAMP_SFT 12
1182 #define RT5640_RAMP_DIS (0x0 << 12)
1183 #define RT5640_RAMP_EN (0x1 << 12)
1192 #define RT5640_MRES_MASK (0x3 << 8)
1193 #define RT5640_MRES_SFT 8
1194 #define RT5640_MRES_15MO (0x0 << 8)
1195 #define RT5640_MRES_25MO (0x1 << 8)
1196 #define RT5640_MRES_35MO (0x2 << 8)
1197 #define RT5640_MRES_45MO (0x3 << 8)
1210 #define RT5640_CP_SYS_MASK (0x7 << 12)
1211 #define RT5640_CP_SYS_SFT 12
1212 #define RT5640_CP_FQ1_MASK (0x7 << 8)
1213 #define RT5640_CP_FQ1_SFT 8
1236 #define RT5640_PM_HP_MASK (0x3 << 8)
1237 #define RT5640_PM_HP_SFT 8
1238 #define RT5640_PM_HP_LV (0x0 << 8)
1239 #define RT5640_PM_HP_MV (0x1 << 8)
1240 #define RT5640_PM_HP_HV (0x2 << 8)
1271 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1272 #define RT5640_MIC2_CLK_SFT 12
1273 #define RT5640_MIC2_CLK_DIS (0x0 << 12)
1274 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1284 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1285 #define RT5640_MIC2_OVCD_SFT 8
1286 #define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1287 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1313 #define RT5640_EQ_DITH_MASK (0x3 << 8)
1314 #define RT5640_EQ_DITH_SFT 8
1315 #define RT5640_EQ_DITH_NOR (0x0 << 8)
1316 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1317 #define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1318 #define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1321 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1322 #define RT5640_EQ_HPF1_M_SFT 8
1323 #define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1324 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1375 #define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1376 #define RT5640_DRC_AGC_AR_SFT 8
1389 #define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1390 #define RT5640_DRC_AGC_POB_SFT 8
1405 #define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1406 #define RT5640_DRC_AGC_NGB_SFT 12
1429 #define RT5640_ANC_MD_MASK (0x3 << 12)
1430 #define RT5640_ANC_MD_SFT 12
1431 #define RT5640_ANC_MD_DIS (0x0 << 12)
1432 #define RT5640_ANC_MD_67MS (0x1 << 12)
1433 #define RT5640_ANC_MD_267MS (0x2 << 12)
1434 #define RT5640_ANC_MD_1067MS (0x3 << 12)
1443 #define RT5640_ANC_ZCD_MASK (0x3 << 8)
1444 #define RT5640_ANC_ZCD_SFT 8
1445 #define RT5640_ANC_ZCD_DIS (0x0 << 8)
1446 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1447 #define RT5640_ANC_ZCD_T2 (0x2 << 8)
1448 #define RT5640_ANC_ZCD_WT (0x3 << 8)
1461 #define RT5640_ANC_FG_R_MASK (0xf << 12)
1462 #define RT5640_ANC_FG_R_SFT 12
1463 #define RT5640_ANC_FG_L_MASK (0xf << 8)
1464 #define RT5640_ANC_FG_L_SFT 8
1500 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1501 #define RT5640_JD_SPL_TRG_SFT 8
1502 #define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1503 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1572 #define RT5640_OT_STKY_MASK (0x1 << 12)
1573 #define RT5640_OT_STKY_SFT 12
1574 #define RT5640_OT_STKY_DIS (0x0 << 12)
1575 #define RT5640_OT_STKY_EN (0x1 << 12)
1616 #define RT5640_GPIO1_STATUS (0x1 << 8)
1631 #define RT5640_GP3_PIN_MASK (0x3 << 12)
1632 #define RT5640_GP3_PIN_SFT 12
1633 #define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1634 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1635 #define RT5640_GP3_PIN_IRQ (0x2 << 12)
1662 #define RT5640_GP3_PF_MASK (0x1 << 8)
1663 #define RT5640_GP3_PF_SFT 8
1664 #define RT5640_GP3_PF_IN (0x0 << 8)
1665 #define RT5640_GP3_PF_OUT (0x1 << 8)
1699 /* FM34-500 Register Control 1 (0xc4) */
1702 /* FM34-500 Register Control 2 (0xc5) */
1705 /* FM34-500 Register Control 3 (0xc6) */
1712 #define RT5640_DSP_CLK_MASK (0x3 << 12)
1713 #define RT5640_DSP_CLK_SFT 12
1714 #define RT5640_DSP_CLK_384K (0x0 << 12)
1715 #define RT5640_DSP_CLK_192K (0x1 << 12)
1716 #define RT5640_DSP_CLK_96K (0x2 << 12)
1717 #define RT5640_DSP_CLK_64K (0x3 << 12)
1728 #define RT5640_DSP_W_EN (0x1 << 8)
1729 #define RT5640_DSP_W_EN_BIT 8
1738 #define RT5640_REG_SEQ_MASK (0xf << 12)
1739 #define RT5640_REG_SEQ_SFT 12
1752 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1753 #define RT5640_SEQ_2_PT_BIT 8
1762 #define RT5640_SEQ_DLY_MASK (0xff << 8)
1763 #define RT5640_SEQ_DLY_SFT 8
1774 #define RT5640_SEQ1_START_MASK (0xf << 8)
1775 #define RT5640_SEQ1_START_SFT 8
1780 #define RT5640_SEQ2_START_MASK (0xf << 8)
1781 #define RT5640_SEQ2_START_SFT 8
1804 #define RT5640_BB_CT_MASK (0x7 << 12)
1805 #define RT5640_BB_CT_SFT 12
1806 #define RT5640_BB_CT_A (0x0 << 12)
1807 #define RT5640_BB_CT_B (0x1 << 12)
1808 #define RT5640_BB_CT_C (0x2 << 12)
1809 #define RT5640_BB_CT_D (0x3 << 12)
1812 #define RT5640_M_BB_R_MASK (0x1 << 8)
1813 #define RT5640_M_BB_R_SFT 8
1830 #define RT5640_EG_MP3_MASK (0x1f << 8)
1831 #define RT5640_EG_MP3_SFT 8
1846 #define RT5640_OG_MP3_MASK (0x1f << 8)
1847 #define RT5640_OG_MP3_SFT 8
1872 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1873 #define RT5640_M_3D_D2H_SFT 8
1884 #define RT5640_HPF_CF_L_MASK (0x7 << 12)
1885 #define RT5640_HPF_CF_L_SFT 12
1890 #define RT5640_HPF_CF_R_MASK (0x7 << 8)
1891 #define RT5640_HPF_CF_R_SFT 8
1951 #define RT5640_HP_SV_MASK (0x1 << 12)
1952 #define RT5640_HP_SV_SFT 12
1953 #define RT5640_HP_SV_DIS (0x0 << 12)
1954 #define RT5640_HP_SV_EN (0x1 << 12)
1966 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1985 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1986 #define RT5640_M_MONO_ADC_R_SFT 12
1990 #define RT5640_IRQ_JD2_MASK (0x1 << 12)
1991 #define RT5640_IRQ_JD2_SFT 12
1992 #define RT5640_IRQ_JD2_BP (0x0 << 12)
1993 #define RT5640_IRQ_JD2_NOR (0x1 << 12)
1998 #define RT5640_JD2_MASK (0x1 << 8)
1999 #define RT5640_JD2_SFT 8
2000 #define RT5640_JD2_DIS (0x0 << 8)
2001 #define RT5640_JD2_EN (0x1 << 8)
2006 #define RT5640_MIC_OVCD_SF_MASK (0x3 << 8)
2007 #define RT5640_MIC_OVCD_SF_SFT 8
2008 #define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8)
2009 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
2010 #define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8)
2011 #define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8)
2020 #define RT5640_3D_SPK_CG_MASK (0x1f << 8)
2021 #define RT5640_3D_SPK_CG_SFT 8
2051 /* Wind Noise Detection Control 8 (0x73) */
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2055 #define RT5640_WND_STRONG_SFT 12