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/linux-6.12.1/include/soc/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
/linux-6.12.1/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
177 #define DA9062AA_GPI4_SHIFT 4
[all …]
/linux-6.12.1/include/linux/mfd/abx500/
Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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/linux-6.12.1/include/linux/mfd/
Dstm32-timers.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/dma-mapping.h>
26 #define TIM_ARR 0x2c /* Auto-Reload Register */
27 #define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */
31 #define TIM_CCR4 TIM_CCRx(4) /* Capt/Comp Register 4 */
32 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
37 #define TIM_CR1_CEN BIT(0) /* Counter Enable */
38 #define TIM_CR1_DIR BIT(4) /* Counter Direction */
39 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
40 #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
[all …]
Drohm-bd71815.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
237 #define BD71815_BUCK_SNVS_ON BIT(3)
238 #define BD71815_BUCK_RUN_ON BIT(2)
239 #define BD71815_BUCK_LPSR_ON BIT(1)
240 #define BD71815_BUCK_SUSP_ON BIT(0)
243 #define BD71815_BUCK_DVSSEL BIT(7)
244 #define BD71815_BUCK_STBY_DVS BIT(6)
[all …]
Dtps65219.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
89 #define TPS65219_REG_INT_SYS_POS 4
103 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
104 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
106 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
107 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
109 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
110 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
111 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
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Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
4 /* Machine-generated file */
9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
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/linux-6.12.1/drivers/net/ethernet/freescale/dpaa2/
Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
18 #define DPKG_NUM_OF_MASKS 4
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
52 * struct dpkg_mask - A structure for defining a single extraction mask
64 #define NH_FLD_ETH_DA BIT(0)
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/linux-6.12.1/drivers/staging/vme_user/
Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
37 void (*lm_callback[4])(void *); /* Called in interrupt handler */
38 void *lm_data[4];
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
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/linux-6.12.1/drivers/phy/mediatek/
Dphy-mtk-mipi-dsi-mt8173.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-io.h"
8 #include "phy-mtk-mipi-dsi.h"
11 #define RG_DSI_LDOCORE_EN BIT(0)
12 #define RG_DSI_CKG_LDOOUT_EN BIT(1)
14 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
17 #define RG_DSI_LPTX_CLMP_EN BIT(11)
24 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
25 #define RG_DSI_LNTx_CKLANE_EN BIT(1)
[all …]
/linux-6.12.1/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
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/linux-6.12.1/drivers/crypto/intel/qat/qat_common/
Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
[all …]
/linux-6.12.1/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
162 #define DA9150_REVERT_MASK BIT(7)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
182 #define DA9150_LFOSC_STAT_MASK BIT(7)
186 #define DA9150_GPIOA_STAT_MASK BIT(0)
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/linux-6.12.1/drivers/gpu/drm/mcde/
Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
[all …]
/linux-6.12.1/sound/soc/codecs/
Dmt6357.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
[all …]
Drk3328_codec.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 #define PIN_DIRECTION_MASK BIT(5)
40 #define DAC_I2S_MODE_MASK BIT(4)
41 #define DAC_I2S_MODE_SLAVE (0x0 << 4)
42 #define DAC_I2S_MODE_MASTER (0x1 << 4)
45 #define DAC_I2S_LRP_MASK BIT(7)
53 #define DAC_MODE_MASK GENMASK(4, 3)
58 #define DAC_LR_SWAP_MASK BIT(2)
68 #define DAC_RST_MASK BIT(1)
71 #define DAC_BCP_MASK BIT(0)
[all …]
Dwcd939x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
15 #define WCD939X_BIAS_ANALOG_BIAS_EN BIT(7)
16 #define WCD939X_BIAS_PRECHRG_EN BIT(6)
17 #define WCD939X_BIAS_PRECHRG_CTL_MODE BIT(5)
19 #define WCD939X_RX_SUPPLIES_VPOS_EN BIT(7)
20 #define WCD939X_RX_SUPPLIES_VNEG_EN BIT(6)
21 #define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL BIT(3)
22 #define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL BIT(2)
23 #define WCD939X_RX_SUPPLIES_REGULATOR_MODE BIT(1)
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/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
Dpwrseq.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
8 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
10 * 0: POFF--Power Off
11 * 1: PDN--Power Down
12 * 2: CARDEMU--Card Emulation
13 * 3: ACT--Active Mode
14 * 4: LPS--Low Power State
15 * 5: SUS--Suspend
46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
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/linux-6.12.1/drivers/platform/x86/intel/pmc/
Dmtl.c1 // SPDX-License-Identifier: GPL-2.0
20 static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
25 * MTL-M SOC-M IOE-M None
26 * MTL-P SOC-M IOE-P None
27 * MTL-S SOC-S IOE-P PCH-S
31 {"PMC", BIT(0)},
32 {"OPI", BIT(1)},
33 {"SPI", BIT(2)},
34 {"XHCI", BIT(3)},
35 {"SPA", BIT(4)},
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/linux-6.12.1/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
58 4 allows tracking up to 5 fingers.
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/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_HT_NSS_MASK GENMASK(4, 3)
18 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
21 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
[all …]
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
[all …]
/linux-6.12.1/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
22 #define TW5864_EMU_EN_SEN BIT(2)
[all …]
/linux-6.12.1/drivers/net/dsa/microchip/
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
12 #define KS_PRIO_S 4
14 /* 0 - Operation */
38 #define SWITCH_REVISION_S 4
43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
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