linux/mfd/stm32-timers.h

1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/dma-mapping.h>
26 #define TIM_ARR		0x2c			/* Auto-Reload Register			*/
27 #define TIM_CCRx(x)	(0x34 + 4 * ((x) - 1))	/* Capt/Comp Register x (x ∈ {1, .. 4})	*/
31 #define TIM_CCR4	TIM_CCRx(4)		/* Capt/Comp Register 4			*/
32 #define TIM_BDTR	0x44			/* Break and Dead-Time Reg		*/
37 #define TIM_CR1_CEN		BIT(0)					/* Counter Enable				*/
38 #define TIM_CR1_DIR		BIT(4)					/* Counter Direction				*/
39 #define TIM_CR1_ARPE		BIT(7)					/* Auto-reload Preload Ena			*/
40 #define TIM_CR2_MMS		(BIT(4) | BIT(5) | BIT(6))		/* Master mode selection			*/
42 #define TIM_SMCR_SMS		(BIT(0) | BIT(1) | BIT(2))		/* Slave mode selection				*/
43 #define TIM_SMCR_TS		(BIT(4) | BIT(5) | BIT(6))		/* Trigger selection				*/
44 #define TIM_DIER_UIE		BIT(0)					/* Update interrupt				*/
45 #define TIM_DIER_CCxIE(x)	BIT(1 + ((x) - 1))			/* CCx Interrupt Enable	(x ∈ {1, .. 4})		*/
49 #define TIM_DIER_CC4IE		TIM_DIER_CCxIE(4)			/* CC4 Interrupt Enable				*/
50 #define TIM_DIER_UDE		BIT(8)					/* Update DMA request Enable			*/
51 #define TIM_DIER_CCxDE(x)	BIT(9 + ((x) - 1))			/* CCx DMA request Enable (x ∈ {1, .. 4})	*/
55 #define TIM_DIER_CC4DE		TIM_DIER_CCxDE(4)			/* CC4 DMA request Enable			*/
56 #define TIM_DIER_COMDE		BIT(13)					/* COM DMA request Enable			*/
57 #define TIM_DIER_TDE		BIT(14)					/* Trigger DMA request Enable			*/
58 #define TIM_SR_UIF		BIT(0)					/* Update interrupt flag			*/
59 #define TIM_SR_CC_IF(x)		BIT((x) + 1)				/* CC1, CC2, CC3, CC4 interrupt flag		*/
60 #define TIM_EGR_UG		BIT(0)					/* Update Generation				*/
61 #define TIM_CCMR_PE		BIT(3)					/* Channel Preload Enable			*/
62 #define TIM_CCMR_M1		(BIT(6) | BIT(5))			/* Channel PWM Mode 1				*/
63 #define TIM_CCMR_CC1S		(BIT(0) | BIT(1))			/* Capture/compare 1 sel			*/
65 #define TIM_CCMR_CC2S		(BIT(8) | BIT(9))			/* Capture/compare 2 sel			*/
67 #define TIM_CCMR_CC1S_TI1	BIT(0)					/* IC1/IC3 selects TI1/TI3			*/
68 #define TIM_CCMR_CC1S_TI2	BIT(1)					/* IC1/IC3 selects TI2/TI4			*/
69 #define TIM_CCMR_CC2S_TI2	BIT(8)					/* IC2/IC4 selects TI2/TI4			*/
70 #define TIM_CCMR_CC2S_TI1	BIT(9)					/* IC2/IC4 selects TI1/TI3			*/
71 #define TIM_CCMR_CC3S		(BIT(0) | BIT(1))			/* Capture/compare 3 sel			*/
72 #define TIM_CCMR_CC4S		(BIT(8) | BIT(9))			/* Capture/compare 4 sel			*/
73 #define TIM_CCMR_CC3S_TI3	BIT(0)					/* IC3 selects TI3				*/
74 #define TIM_CCMR_CC4S_TI4	BIT(8)					/* IC4 selects TI4				*/
75 #define TIM_CCER_CCxE(x)	BIT(0 + 4 * ((x) - 1))			/* Capt/Comp x  out Ena (x ∈ {1, .. 4})		*/
76 #define TIM_CCER_CCxP(x)	BIT(1 + 4 * ((x) - 1))			/* Capt/Comp x  Polarity (x ∈ {1, .. 4})	*/
77 #define TIM_CCER_CCxNE(x)	BIT(2 + 4 * ((x) - 1))			/* Capt/Comp xN out Ena (x ∈ {1, .. 4})		*/
78 #define TIM_CCER_CCxNP(x)	BIT(3 + 4 * ((x) - 1))			/* Capt/Comp xN Polarity (x ∈ {1, .. 4})	*/
91 #define TIM_CCER_CC4E		TIM_CCER_CCxE(4)			/* Capt/Comp 4  out Ena				*/
92 #define TIM_CCER_CC4P		TIM_CCER_CCxP(4)			/* Capt/Comp 4  Polarity			*/
93 #define TIM_CCER_CC4NE		TIM_CCER_CCxNE(4)			/* Capt/Comp 4N out Ena				*/
94 #define TIM_CCER_CC4NP		TIM_CCER_CCxNP(4)			/* Capt/Comp 4N Polarity			*/
95 #define TIM_CCER_CCXE		(BIT(0) | BIT(4) | BIT(8) | BIT(12))
96 #define TIM_BDTR_BKE(x)		BIT(12 + (x) * 12)			/* Break input enable				*/
97 #define TIM_BDTR_BKP(x)		BIT(13 + (x) * 12)			/* Break input polarity				*/
98 #define TIM_BDTR_AOE		BIT(14)					/* Automatic Output Enable			*/
99 #define TIM_BDTR_MOE		BIT(15)					/* Main Output Enable				*/
100 #define TIM_BDTR_BKF(x)		(0xf << (16 + (x) * 4))
101 #define TIM_DCR_DBA		GENMASK(4, 0)				/* DMA base addr				*/
106 #define TIM_CR2_MMS_SHIFT			4
112 #define TIM_SMCR_TS_SHIFT			4
114 #define TIM_BDTR_BKF_SHIFT(x)			(16 + (x) * 4)
127 /* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */
137  * struct stm32_timers_dma - STM32 timer DMA handling.
174 	return -ENODEV;  in stm32_timers_dma_burst_read()